Issue No. 08 - August (1994 vol. 5)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/71.298211
<p>Considers the use of massively parallel architectures to execute a trace-driven simulation of a single cache set. A method is presented for the least-recently-used (LRU) policy, which, regardless of the set size C, runs in time O(log N) using N processors on the EREW (exclusive read, exclusive write) parallel model. A simpler LRU simulation algorithm is given that runs in O(C log N) time using N/log N processors. We present timings of this algorithm's implementation on the MasPar MP-1, a machine with 16384 processors. A broad class of reference-based line replacement policies are considered, which includes LRU as well as the least-frequently-used (LFU) and random replacement policies. A simulation method is presented for any such policy that, on any trace of length N directed to a C line set, runs in O(C log N) time with high probability using N processors on the EREW model. The algorithms are simple, have very little space overhead, and are well suited for SIMD implementation.</p>
Index Termsparallel algorithms; buffer storage; parallel architectures; computational complexity; program diagnostics; massively parallel algorithms; trace-driven cache simulations; least-recently-used policy; EREW parallel model; simulation algorithm; algorithm timings; MasPar MP-1; reference-based line replacement policies; least-frequently-used policy; random replacement policy; trace; space overhead; SIMD implementation
B. Lubachevsky, D. Nicol and A. Greenberg, "Massively Parallel Algorithms for Trace-Driven Cache Simulations," in IEEE Transactions on Parallel & Distributed Systems, vol. 5, no. , pp. 849-859, 1994.