Issue No. 07 - July (1994 vol. 5)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/71.296316
<p>A new architecture is presented to support the general class of real-timelarge-vocabulary speaker-independent continuous speech recognizers incorporatinglanguage models. Many such recognizers require multiple high-performance centralprocessing units (CPU's) as well as high interprocessor communication bandwidth. Thisarray processor provides a peak CPU performance of 2.56 giga-floating point operationsper second (GFLOPS) as well as a high-speed communication network. In order toefficiently utilize these resources, algorithms were devised for partitioning speech modelsfor mapping into the array processor. Also, a novel scheme is presented for a functionalpartitioning of the speech recognizer computations. The recognizer is functionallypartitioned into six stages, namely, the linear predictive coding (LPC) based featureextractor, mixture probability computer, (phone) state probability computer, wordprobability computer, phrase probability computer, and traceback computer. Each ofthese stages is further subdivided as many times as necessary to fit the individualprocessing elements (PE's). The functional stages are pipelined and synchronized with the frame rate of the incoming speech signal. This partitioning also allows a multistage stack decoder to be implemented for reduction of computation.</p>
Index Termslinear predictive coding; array signal processing; parallel architectures; speechrecognition; message passing; spoken language recognition; DSP array processor;real-time large-vocabulary speaker-independent continuous speech recognizers; multiplehigh-performance central processing units; high interprocessor communication bandwidth; array processor; partitioning; linear predictive coding; feature extractor; mixture probability computer; state probability computer; word probability computer; phrase probability computer; traceback computer; multistage stack decoder
S. Glinski and D. Roe, "Spoken Language Recognition on a DSP Array Processor," in IEEE Transactions on Parallel & Distributed Systems, vol. 5, no. , pp. 697-703, 1994.