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Issue No. 06 - June (1994 vol. 5)
ISSN: 1045-9219
pp: 658-664
ABSTRACT
<p>This short note describes issues involved in the bypassing mechanism for a very longinstruction word (VLIW) processor and its relation to the pipeline structure of theprocessor. The authors first describe the pipeline structure of their processor and analyzeits performance and compare it to typical RISC-style pipeline structures given the contextof a processor with multiple functional units. Next they study the performance effects ofvarious bypassing schemes in terms of their effectiveness in resolving pipeline data hazards and their effect on the processor cycle time.</p>
INDEX TERMS
Index Termsparallel architectures; pipeline processing; performance evaluation; bypassing; VLIWprocessor; very long instruction word; pipeline structure; performance; pipeline data hazards; computer architecture
CITATION
N. Bagherzadeh, A. Abnous, "Pipelining and Bypassing in a VLIW Processor", IEEE Transactions on Parallel & Distributed Systems, vol. 5, no. , pp. 658-664, June 1994, doi:10.1109/71.285612
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