The Community for Technology Leaders
Green Image
<p>For memory bandwidth analysis, researchers generally discard requests that are notaccepted during a memory cycle. This assumption simplifies the analysis and producesnegligible discrepancies with actual results for a system with a non-hierarchicalinterconnection network. However, the assumption, "the requests that are not occupiedduring a memory cycle are discarded," cannot be used for a multiprocessor system with ahierarchical interconnection network (HIN), because the error introduced assumption canbe several orders of magnitude higher than the actual bandwidth. An improved analyticalmodel to determine the bandwidth of a HIN-based system is presented.</p>
Index Termsmultiprocessor interconnection networks; memory architecture; shared memory systems;performance evaluation; failure analysis; memory bandwidth analysis; hierarchicalmultiprocessors; model decomposition; steady-state flow analysis; memory cycle;hierarchical interconnection network
L.T. Samaratunga, S.M. Mahmud, "Memory Bandwidth Analysis of Hierarchical Multiprocessors using Model Decomposition and Steady-State Flow Analysis", IEEE Transactions on Parallel & Distributed Systems, vol. 5, no. , pp. 553-560, May 1994, doi:10.1109/71.282567
94 ms
(Ver 3.3 (11022016))