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<p>Computer architectures supporting shared memory continue to increase in complexity asdesigners seek to improve memory performance. This is especially true of proposals formassively parallel systems with distributed, yet shared, memory. The need to maintain areasonably simple memory model for programmers, in spite of enhancements like cachesand access pipelining, is responsible for many of the complications. We develop a novelgraph model, access graphs, for visualizing processor/memory interaction. Access graphssymbolically represent the causal relationships between load, store, and synchronizationevents. The focus is on two classes of access graphs: pseudo and real. A pseudo accessgraph describes an execution in terms of abstract events familiar to the programmer. Ifthe pseudo access graph is acyclic, then memory consistency is preserved during theexecution. A real access graph describes an execution in terms of physical events knownto the hardware designer. A real access graph must be acyclic since hardware cannotviolate causality. Memory consistency can be verified for a given computer system byproving that for any acyclic real access graph describing a program's execution on thatcomputer, an acyclic pseudo access graph can be derived describing the same execution.</p>
Index Termsshared memory systems; computer architecture; synchronisation; memory consistency;computer architectures; massively parallel systems; caches; access pipelining;synchronization

D. Linder and J. Harden, "Access Graphs: A Model for Investigating Memory Consistency," in IEEE Transactions on Parallel & Distributed Systems, vol. 5, no. , pp. 39-52, 1994.
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