Issue No. 10 - October (1993 vol. 4)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/71.246074
<p>Efficiently maintaining cache coherence is a major problem in large-scale shared memorymultiprocessors. Hardware directory coherence schemes have very high memoryrequirements, while software-directed schemes must rely on imprecise compile-timememory disambiguation. Recently proposed dynamically tagged directory schemes allocate pointers to blocks only as they are referenced, which significantly reduces their memory requirements, but they still allocate pointers to blocks that do not need them. Theauthors present two compiler optimizations that exploit the high-level sharing information available to the compiler to further reduce the size of a tagged directory by allocating pointers only when necessary. Trace-driven simulations are used to show that the performance of this combined hardware-software approach is comparable to othercoherence schemes, but with significantly lower memory requirements. In addition, thesesimulations suggest that this approach is less sensitive to the quality of the memorydisambiguation and interprocedural analysis performed by the compiler than software-only coherence schemes.</p>
Index Termsmemory utilization; cache coherence directories; large-scale shared memorymultiprocessors; software-directed schemes; compile-time memory disambiguation;dynamically tagged directory; compiler optimizations; high-level sharing information;trace-driven simulations; interprocedural analysis; buffer storage; configurationmanagement; discrete event simulation; program compilers; shared memory systems;storage allocation
D. Lilja and P. Yew, "Improving Memory Utilization in Cache Coherence Directories," in IEEE Transactions on Parallel & Distributed Systems, vol. 4, no. , pp. 1130-1146, 1993.