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<p>Describes and analyzes the Hybrid Array Ring Processor (HARP) architecture. The HARP is an application specific architecture built around a host processor, shared memory, and a set of memory mapped processing cells that are connected both into an open backplane and a bidirectional systolic ring. The architecture is analyzed through detailed simulation of a system implementation based on the Texas Instruments TMS34082 floating point RISC. A bus controller is designed that provides a tightly coupled DMA function that accelerates systolic communication and supports new interleaved transparent communications and reduced overhead message passing. The architecture is benchmarked with the matrix multiplication, FFT, QRD, and SVD algorithms.</p>
Index TermsHARP; open architecture; signal processing; matrix processing; Hybrid Array RingProcessor; parallel; shared memory; memory mapped processing cells; open backplane;bidirectional systolic ring; bus controller; DMA function; systolic communication;Application specific architecture; reduced overhead message passing; digital signalprocessor; interprocessor communication; multiprocessor; parallel algorithms; systolicarray; parallel architectures; shared memory systems; signal processing; systolic arrays
R.S. Drafz, Z. Fu, E.M. Dowling, "HARP: An Open Architecture for Parallel Matrix and Signal Processing", IEEE Transactions on Parallel & Distributed Systems, vol. 4, no. , pp. 1081-1091, October 1993, doi:10.1109/71.246070
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