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<p>The butterfly parallel system has a regular and simple interconnection pattern, making itsuitable for VLSI or WSI implementation. The authors propose an effective fault-toleranttechnique for the circular butterfly parallel system to ensure its rigid full butterflystructure even in the presence of failures, addressing reconfiguration in detail. Theresulting butterfly system has L levels, involves (1/log/sub 2/ L)% spare processingelements (PEs), and approximately 50% additional links. The reconfiguration process ofthe design in response to any operational fault is easy and can be performed in adistributed manner. The reliability and layout of this proposed design are evaluatedanalytically. This design, due to its specific configuration, exhibits significant improvement in reliability while taking only moderately more layout area.</p>
Index Termsfault-tolerant circular butterfly parallel system; interconnection pattern; VLSI; WSI;reconfiguration; spare processing elements; fault tolerant computing; multiprocessorinterconnection networks; reconfigurable architectures

N. Tzeng, "Reconfiguration and Analysis of a Fault-Tolerant Circular Butterfly Parallel System," in IEEE Transactions on Parallel & Distributed Systems, vol. 4, no. , pp. 855-863, 1993.
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