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The performance evaluation of processor-memory communications for multiprocessor systems using circuit switched interconnection networks with a hold strategy is performed. Message size and processor processing time are considered and shown to have a significant effect on the overall system performance. A closed queuing network model is proposed such that only (n+2) states are required by the proposed model, in contrast to (n/sup 2/+3n+4)/2 states needed in previous studies, where n is the number of stages of the multistage interconnection network. Since a closed-form solution is obtained, the behavior of a complete cycle of memory access through multistage interconnection networks can be accurately analyzed and various performance bounds can be obtained.
Index Termsmessage size; circuit switched multistage interconnection networks; hold strategy;performance evaluation; processor-memory communications; multiprocessor systems;processor processing time; closed queuing network model; memory access;multiprocessor interconnection networks; performance evaluation; queueing theory;switching theory

S. Hsiao and C. Chen, "Performance Evaluation of Circuit Switched Multistage Interconnection Networks Using a Hold Strategy," in IEEE Transactions on Parallel & Distributed Systems, vol. 3, no. , pp. 632-640, 1992.
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