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Multicomputer cache simulation results derived from address traces collected from an Intel iPSC/2 hypercube multicomponent are presented. The primary emphasis is on examining how increasing the number of processor nodes executing a parallel application affects the overall multicomputer cache performance. The effects on multicomputer direct-mapped cache performance of application-specific data partitioning, data access patterns, communication distribution, and communication frequency are illustrated. The effects of system accesses on total cache performance are explored, as well as the reasons for application-specific differences in cache behavior for system and user accesses. Comparing user code results with full user and system code analysis reveals the significant effect of system accesses, and this effect increases with multicomputer size. The time distribution of an application's message-passing operations is found to more strongly affect cache performance than the total amount of time spent in message-passing code.
Index Termshypercube multicomputer; cache simulation; address traces; Intel iPSC/2; processornodes; parallel application; direct-mapped cache performance; application-specific datapartitioning; data access patterns; communication distribution; communication frequency;system accesses; user code; code analysis; time distribution; message-passing code;buffer storage; hypercube networks; parallel programming; performance evaluation;storage management

C. Stunkel and W. Fuchs, "An Analysis of Cache Performance for a Hypercube Multicomputer," in IEEE Transactions on Parallel & Distributed Systems, vol. 3, no. , pp. 421-432, 1992.
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