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An application-specific architecture for the parallel calculation of the decimation in time and radix 2 fast Hartley (FHT) and Fourier (FFT) transforms is presented. A real sequence with N=2/sup n/ data items is considered as input. The system calculates the FHT and the FFT in n and n+1 stages. respectively. The modular and regular parallel architecture is based on a constant geometry algorithm using butterflies of four data items and the perfect unshuffle permutation. With this permutation, the mapping of the algorithm in VLSI technology is simplified and the communications among processors are minimized. Organization of the processor memory based on first-in, first-out (FIFO) queues facilitates a systolic data flow and permits the implementation in a direct way of the complex data movements and address sequences of the transforms. This is accomplished by means of simple multiplexing operations, using hardwired control. The total calculation time is (Nlog/sub 2/N)/4Q cycles for the FHT and N(1+log/sub 2/N)/4Q cycles for the FFT, where Q is the number of processors (Q= 2/sup q/, Q>or=N/4).
Index Termsfast Hartley transform; fast Fourier transform; FIFO queues; VLSI constant geometryarchitecture; application-specific architecture; parallel calculation; parallel architecture;constant geometry algorithm; butterflies; perfect unshuffle permutation; processormemory; systolic data flow; multiplexing operations; hardwired control; computationalcomplexity; fast Fourier transforms; parallel algorithms; parallel architectures; VLSI

E. Zapata and F. Argüello, "A VLSI Constant Geometry Architecture for the Fast Hartley and Fourier Transforms," in IEEE Transactions on Parallel & Distributed Systems, vol. 3, no. , pp. 58-70, 1992.
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