Issue No. 01 - January (1992 vol. 3)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/71.113079
Pin minimization is an important issue for massively parallel architectures because the number of processing elements that can be placed on a chip, board, or chassis is often pin limited. A d-dimensional bused hypercube interconnection network is presented that allows nodes to simultaneously (in one clock tick) exchange data across any dimension using only d+1 ports per node rather than 2d. Despite this near two-to-one reduction, the network also allows nodes that are two dimensions apart to simultaneously exchange data; as a result, certain routings can be performed in nearly half the time. The network is shown to be a special case of a general construction in which any set of d permutations can be performed, in one clock tick, using only d+1 ports per node. A lower-bound technique is also presented and used to establish the optimality of the network, as well as that of several other new bused networks.
Index Termspin minimisation; simultaneous data exchange; pin-optimal networks; massively parallelarchitectures; processing elements; chip; board; chassis; bused hypercubeinterconnection network; clock tick; ports; hypercube networks
C.M. Fiduccia, "Bused Hypercubes and Other Pin-Optimal Networks", IEEE Transactions on Parallel & Distributed Systems, vol. 3, no. , pp. 14-24, January 1992, doi:10.1109/71.113079