DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2013.81
Naoya Onizawa , McGill University, Montreal
Atsushi Matsumoto , Tohoku University, Sendai
Tomoyoshi Funazaki , Tohoku University, Sendai
Takahiro Hanyu , Tohoku University, Sendai
A new asynchronous delay-insensitive data-transmission method based on level-encoded dual-rail (LEDR) encoding with novel packet-structure restriction is proposed to realize a high-throughput Network-on-Chip (NoC) router together with a compact hardware. The use of LEDR encoding makes communication steps and the registers being used half in comparison with four-phase dual-rail encoding, be- cause the spacer information of the four-phase one is eliminated, which significantly improves the network throughput. By using the proposed packet structure, the phase information of header and tail flits is uniquely determined. Since the router can be asynchronously controlled by ignoring the phase information, the circuit is compactly implemented. As a result, the proposed asynchronous NoC router on a 0.13&#x03BC;m CMOS technology, has a 90% increase in throughput and a 34% decrease in energy dissipation with 25% area overhead in comparison with a conventional four-phase asynchronous NoC router under a post-layout simulation. In a 4x4 2-D mesh topology, the proposed asynchronous NoC has a 140% increase in throughput and half packet latency compared with the conventional one. We also fabricate the asynchronous NoC based on the proposed router on a 0.13&#x03BC;m CMOS technology and demonstrate the chip correctly operates under a supply voltage of 0.6V to 1.8V.
Interprocessor communications, Hardware, Logic Design, Design Styles, Integrated Circuits, General, Computer Systems Organization, Processor Architectures, Parallel Architectures, On-chip interconnection networks, Communication/Networking and Information Technology
N. Onizawa, A. Matsumoto, T. Funazaki and T. Hanyu, "High-Throughput Compact Delay-Insensitive Asynchronous NoC Router," in IEEE Transactions on Computers.