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Issue No. 02 - Feb. (2018 vol. 67)
ISSN: 0018-9340
pp: 291-298
Jagannath Samanta , Haldia Institute of Technology, Haldia, West Bengal, India
Jaydeb Bhaumik , Haldia Institute of Technology, Haldia, West Bengal, India
Soma Barman , Institute of Radio Physics and Electronics, University of Calcutta, Kolkata, West Bengal, India
Memory contents are usually corrupted due to soft errors caused by external radiation and hence the reliability of memory systems is reduced. In order to enhance the reliability of memory systems, error correcting codes (ECC) are widely used to detect and correct errors. Single bit error correcting with double bits errors detecting codes are generally used in memory systems. But in case of multiple cell errors, these codes are unable to detect and correct errors. Recently, single byte error correcting Reed Solomon (SEC-RS) codes are used to detect and correct single byte error in memory systems. In this paper, a new single byte error correcting (SEC) code is proposed based on the concept of cellular automata (termed as CASEC). The main aim of this work is to reduce the area and power of SEC encoder and decoder circuit without affecting delay. In this paper, CASEC(10,8,8), CASEC(18,16,8), 2xCASEC(10,8,4) and 2xCASEC(19,6,4) codecs are designed and implemented. CASEC(18,16,8) codec has 67.79 percent lesser hardware complexity compared to existing design. Proposed codecs are simulated and synthesized for both FPGA and ASIC platforms. It is found that speed of the proposed design is almost equal to the existing design but requires lesser area and power. Area-delay product (ADP) of proposed CASEC(10,8,8), CASEC(18,16,8), 2xCASEC(10,8,4) codecs are better compared to the existing designs.
Error correction codes, Codecs, Delays, Parity check codes, Computer architecture, Decoding, Encoding

J. Samanta, J. Bhaumik and S. Barman, "Compact CA-Based Single Byte Error Correcting Codec," in IEEE Transactions on Computers, vol. 67, no. 2, pp. 291-298, 2018.
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