Issue No. 12 - Dec. (2017 vol. 66)
H. Fatih Ugurdag , Department of Electrical Engineering, Ozyegin University, Istanbul, Turkey
Florent de Dinechin , Institut National des Sciences Appliquées, Lyon, France
Y. Serhan Gener , Department of Computer Engineering, Yeditepe University, Istanbul, Turkey
Sezer Goren , Department of Computer Engineering, Yeditepe University, Istanbul, Turkey
Laurent-Stephane Didier , Université du Sud Toulon Var, La Garde, France
This article studies the design of custom circuits for division by a small positive constant. Such circuits can be useful for specific FPGA and ASIC applications. The first problem studied is the Euclidean division of an unsigned integer by a constant, computing a quotient and remainder. Several new solutions are proposed and compared against the state-of-the-art. As the proposed solutions use small look-up tables, they match well with the hardware resources of an FPGA. The article then studies whether the division by the product of two constants is better implemented as two successive dividers or as one atomic divider. It also considers the case when only a quotient or only a remainder is needed. Finally, it addresses the correct rounding of the division of a floating-point number by a small integer constant. All these solutions, and the previous state-of-the-art, are compared in terms of timing, area, and area-timing product. In general, the relevance domains of the various techniques are different on FPGA and on ASIC.
Field programmable gate arrays, Table lookup, Hardware, Generators, Program processors
H. F. Ugurdag, F. de Dinechin, Y. S. Gener, S. Goren and L. Didier, "Hardware Division by Small Integer Constants," in IEEE Transactions on Computers, vol. 66, no. 12, pp. 2097-2110, 2017.