Issue No. 12 - Dec. (2017 vol. 66)
Xiaoping Cui , College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, China
Wenwen Dong , College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, China
Weiqiang Liu , College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, China
Earl E. Swartzlander , Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX
Fabrizio Lombardi , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA
A parallel decimal multiplier with improved performance is proposed in this paper by exploiting the properties of three different binary coded decimal (BCD) codes, namely the redundant BCD excess-3 code (XS-3), the overloaded decimal digit set (ODDS) code and the BCD-4221/5211 code. The signed-digit radix-10 recoding is used to recode the BCD multiplier to the digit set [-5, 5] from [0, 9]. The redundant BCD XS-3 code is adopted to generate the multiplicand multiples in a carry-free manner. The XS-3 coded partial products (PPs) are converted to ODDS PPs to fit binary partial product reduction (PPR). In this paper, a regular decimal PPR tree using ODDS and BCD-4221/5211 codes is proposed; it consists of a binary PPR tree block, a non-fixed size BCD-4221 counter block and a BCD-4221/5211 PPR tree block. The decimal carry-save algorithm based on BCD-4221/5211 is used in the PPR tree to obtain high performance multipliers. Moreover, an improved PPG circuit and an improved parallel prefix/carry-select decimal adder are proposed to further improve the performance of the proposed multipliers. Analysis and comparison using the 45 nm technology show that the proposed decimal multipliers are faster and require less hardware area than previous designs found in the technical literature.
Adders, Encoding, Electronic mail, Radiation detectors, Hardware, Indexes, Computers
X. Cui, W. Dong, W. Liu, E. E. Swartzlander and F. Lombardi, "High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes," in IEEE Transactions on Computers, vol. 66, no. 12, pp. 1994-2004, 2017.