Issue No. 12 - Dec. (2017 vol. 66)
Martin Langhammer , Intel Programmable Solutions Group, High Wycombe, United Kingdom
Bogdan Pasca , Intel Programmable Solutions Group, Toulouse, France
In this article we present a novel method for implementing floating point (FP) elementary functions using the new FP single precision addition and multiplication features of the Arria 10 and Stratix 10 DSP Block architecture. Our application examples are
and $_$\log (x)$_$ , two of the most commonly required functions for emerging datacenter and computing FPGA targets. We explain why the combination of new FPGA technology, and at the same time, a massive increase in computing performance requirement, fuels the need for this work. We show a comprehensive error analysis, and discuss various implementation trade-offs that demonstrate that the hard FP (HFP) Blocks, in conjunction with the traditional flexibility and connectivity of the FPGA, can provide a robust and high performance solution. The architectures presented in this work meet OpenCL accuracy requirements. Our methods map extensively to embedded structures, and therefore result in significant reduction in logic resources and routing stress compared to current methods. The methods allow leveraging the routing architectures introduced in the Stratix 10 device which results in high-function performance. $_$\exp (x)$_$
Field programmable gate arrays, Digital signal processing, Computer architecture, Performance evaluation, Routing
M. Langhammer and B. Pasca, "Single Precision Logarithm and Exponential Architectures for Hard Floating-Point Enabled FPGAs," in IEEE Transactions on Computers, vol. 66, no. 12, pp. 2031-2043, 2017.