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Issue No. 11 - Nov. (2017 vol. 66)
ISSN: 0018-9340
pp: 1865-1877
Reza Hojabr , Department of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran
Mehdi Modarressi , Department of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran
Masoud Daneshtalab , Royal Institute of Technology (KTH), Stockholm, Sweden
Ali Yasoubi , Department of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran
Ahmad Khonsari , Department of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran
ABSTRACT
Large-scale neural network accelerators are often implemented as a many-core chip and rely on a network-on-chip to manage the huge amount of inter-neuron traffic. The baseline and different variations of the well-known mesh and tree topologies are the most popular topologies in prior many-core implementations of neural networks. However, the grid-like mesh and hierarchical tree topologies suffer from high diameter and low bisection bandwidth, respectively. In this paper, we present ClosNN, a customized Clos topology for Neural N etworks. The inherent capability of Clos to support multicast and broadcast traffic in a simple and efficient way, as well as its adaptable bisection bandwidth, is the major motivation behind proposing a customized version of this topology as the communication infrastructure of large-scale neural network implementations. We compare ClosNN with some state-of-the-art NoC topologies adopted in recent neural network hardware accelerators and show that it offers lower average message hop count and higher throughput, which directly translates to faster neural information processing.
INDEX TERMS
Biological neural networks, Network topology, Topology, Bandwidth, Hardware, Neurons,Neural networks, collective communication, clos topology, network-on-chip
CITATION
Reza Hojabr, Mehdi Modarressi, Masoud Daneshtalab, Ali Yasoubi, Ahmad Khonsari, "Customizing Clos Network-on-Chip for Neural Networks", IEEE Transactions on Computers, vol. 66, no. , pp. 1865-1877, Nov. 2017, doi:10.1109/TC.2017.2715158
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