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Issue No. 11 - Nov. (2017 vol. 66)
ISSN: 0018-9340
pp: 1975-1981
Wei Shu , Center for Advanced Computer Studies, University of Louisiana, Lafayette, LA
Nian-Feng Tzeng , Center for Advanced Computer Studies, University of Louisiana, Lafayette, LA
ABSTRACT
To lower on-chip SRAM area overhead for chip multiprocessors (CMPs), this work treats a novel directory design which compresses present-bit vectors (PVs) by dropping “runs of zeros” commonly existing and lets PVs be transformed to their variations after sharer relinquishment for hashing alternative table sets to lift table utilization. Featured with relinquishment c oherence and compressed sharer t racking (ReCoST), the proposed design attains superior directory efficiency and maintains “exact” directory representations, as a result of dropping abound long runs of zeros present in PVs. According to full-system simulation using gem5 for a range of core counts under PARSEC benchmarks, ReCoST is found to enjoy 3.21 $\times$ (or 2.64$\times$ ) more efficiency in directory storage than conventional bit-tracking directories (or the best directory known so far, called SCD) for a 64-core CMP under monotasking (or multitasking) workloads while ensuring execution slowdowns to stay within 2.4 percent (or 3.3 percent).
INDEX TERMS
Coherence, Benchmark testing, Multitasking, Message systems, Kernel, Radiation detectors, Parallel processing,Chip multi-processors, coherence protocols, directory storage, hashing keys, multitasking, present-bit vectors
CITATION
Wei Shu, Nian-Feng Tzeng, "Compressed Sharer Tracking and Relinquishment Coherence for Superior Directory Efficiency of Chip Multiprocessors", IEEE Transactions on Computers, vol. 66, no. , pp. 1975-1981, Nov. 2017, doi:10.1109/TC.2017.2698043
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