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Issue No. 09 - Sept. (2017 vol. 66)
ISSN: 0018-9340
pp: 1504-1517
Hyunggoy Oh , Department of Electrical and Electronics Engineering, Yonsei University, Seoul, Korea
Inhyuk Choi , Department of Electrical and Electronics Engineering, Yonsei University, Seoul, Korea
Sungho Kang , Department of Electrical and Electronics Engineering, Yonsei University, Seoul, Korea
ABSTRACT
In the post-silicon debug of multicore designs, the debug time has increased significantly because the number of cores undergoing debug has increased; however the resources available to debug the design are limited. This paper proposes a new DRAM-based error detection method to overcome this challenge. The proposed method requires only three debug sessions even if multiple cores are present. The first debug session is used to detect the error intervals of each core using golden signatures. The second session is used to detect the error clock cycles in each core using a golden data stream. Instead of storing all of the golden data, the golden data stream is generated by selecting error-free debug data for each interval which are guaranteed by the first session. Finally, the error data in all cores are only captured during the third session. The experimental results on various debug cases show significant reductions in total debug time and the amount of DRAM usage compared to previous methods.
INDEX TERMS
Multicore processing, Random access memory, Clocks, System-on-chip, Compaction, Debugging, Silicon,Multiple identical cores, DRAM-based debug method, MISR compaction, golden data stream, debug time
CITATION
Hyunggoy Oh, Inhyuk Choi, Sungho Kang, "DRAM-Based Error Detection Method to Reduce the Post-Silicon Debug Time for Multiple Identical Cores", IEEE Transactions on Computers, vol. 66, no. , pp. 1504-1517, Sept. 2017, doi:10.1109/TC.2017.2678504
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