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Issue No. 08 - Aug. (2017 vol. 66)
ISSN: 0018-9340
pp: 1428-1434
Wongyu Shin , Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea
Jaemin Jang , Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea
Jungwhan Choi , Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea
Jinwoong Suh , Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea
Lee-Sup Kim , Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea
ABSTRACT
DDR4 SDRAM introduced a new hierarchy in DRAM organization: bank-group (BG). The main purpose of BG is to increase I/O bandwidth without growing DRAM-internal bus-width. We, however, found that other benefits can be derived from the new hierarchy. To achieve the benefits, we propose a new DRAM architecture using the BG-hierarchy, leading to a creation of BG-Level Parallelism (BGLP). By exploiting BGLP, the overall parallelism grows in DRAM operations. We also argue that BGLP is a feasible solution in the cost-sensitive DRAM industry because the additional cost is negligible and only cost-insensitive area needs to be modified.
INDEX TERMS
Parallel processing, Writing, Computer architecture, Switches, SDRAM, Organizations,DRAM, bank-group level parallelism (BGLP), column-buffer (CoB), main memory
CITATION
Wongyu Shin, Jaemin Jang, Jungwhan Choi, Jinwoong Suh, Lee-Sup Kim, "Bank-Group Level Parallelism", IEEE Transactions on Computers, vol. 66, no. , pp. 1428-1434, Aug. 2017, doi:10.1109/TC.2017.2665475
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