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Issue No. 08 - Aug. (2017 vol. 66)
ISSN: 0018-9340
pp: 1407-1420
Phuong Hoai Ha , Department of Computer Science, Faculty of Science, University of Tromsų, Tromsø, Norway
Philippas Tsigas , Department of Computer Science and Engineering, Chalmers University of Technology, Gothenburg, Sweden
Otto J. Anshus , Department of Computer Science, Faculty of Science, University of Tromsų, Tromsø, Norway
The fact that graphics processors (GPUs) are today’s most powerful computational hardware for the dollar has motivated researchers to utilize the ubiquitous and powerful GPUs for general-purpose computing. However, unlike CPUs, GPUs are optimized for processing 3D graphics (e.g., graphics rendering), a kind of data-parallel applications, and consequently, several GPUs do not support strong synchronization primitives to coordinate their cores. This prevents the GPUs from being deployed more widely for general-purpose computing. This paper aims at bridging the gap between the lack of strong synchronization primitives in the GPUs and the need for strong synchronization mechanisms in parallel applications. Based on the intrinsic features of typical GPU architectures, we construct strong synchronization objects such as wait-free and $_$t$_$ -resilient read-modify-write objects for a general model of GPU architectures without hardware synchronization primitives such as test-and-set and compare-and-swap. Accesses to the wait-free objects have time complexity $_$O(N)$_$ , where $_$N$_$ is the number of processes. The wait-free objects have the optimal space complexity $_$O(N^2)$_$ . Our result demonstrates that it is possible to construct wait-free synchronization mechanisms for GPUs without strong synchronization primitives in hardware and that wait-free programming is possible for such GPUs.
Registers, Graphics processing units, Instruction sets, Synchronization, Proposals, Computer architecture, Hardware

P. H. Ha, P. Tsigas and O. J. Anshus, "Wait-Free Programming for General Purpose Computations on Graphics Processors," in IEEE Transactions on Computers, vol. 66, no. 8, pp. 1407-1420, 2017.
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