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Issue No. 08 - Aug. (2016 vol. 65)
ISSN: 0018-9340
pp: 2534-2547
K. Raghavendra , Department Computer Science and Engineering, Indian Institute of Technology Madras, Chennai, India
Biswabandan Panda , Department Computer Science and Engineering, Indian Institute of Technology Madras, Chennai, India
Madhu Mutyam , Department Computer Science and Engineering, Indian Institute of Technology Madras, Chennai, India
ABSTRACT
Cache compression improves the performance of a multi-core system by being able to store more cache blocks in a compressed format. Compression is achieved by exploiting data patterns present within a block. For a given cache space, compression increases the effective cache capacity. However, this increase is limited by the number of tags that can be accommodated at the cache. Prefetching is another technique that improves system performance by fetching the cache blocks ahead of time into the cache and hiding the off-chip latency. Commonly used hardware prefetchers, such as stream and stride, fetch multiple contiguous blocks into the cache. In this paper we propose prefetched blocks compaction (PBC) wherein we exploit the data patterns present across these prefetched blocks. PBC compacts the prefetched blocks into a single block with a single tag, effectively increasing the cache capacity. We also modify the cache organization to access these multiple cache blocks residing in a single block without any need for extra tag look-ups. PBC improves the system performance by 11.1 percent with a maximum of 43.4 percent on a four-core system.
INDEX TERMS
Prefetching, Compaction, Yttrium, Encoding, Indexes, Hardware, Organizations,prefetching, Memory structures, cache memories, compression, compaction, cache design
CITATION
K. Raghavendra, Biswabandan Panda, Madhu Mutyam, "PBC: Prefetched Blocks Compaction", IEEE Transactions on Computers, vol. 65, no. , pp. 2534-2547, Aug. 2016, doi:10.1109/TC.2015.2493533
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