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Issue No. 07 - July (2016 vol. 65)
ISSN: 0018-9340
pp: 2169-2183
Jun Yang , Data Storage Institute, A-STAR, Singapore
Qingsong Wei , Data Storage Institute, A-STAR, Singapore
Chundong Wang , Data Storage Institute, A-STAR, Singapore
Cheng Chen , Data Storage Institute, A-STAR, Singapore
Khai Leong Yong , Data Storage Institute, A-STAR, Singapore
Bingsheng He , , School of Computer Science and Engineering, Singapore
ABSTRACT
The non-volatile memory (NVM) which can provide DRAM-like performance and disk-like persistency has the potential to build single-level systems by replacing both DRAM and disk. Keeping data consistency in such systems is non-trivial because memory writes may be reordered by CPU. Although ordered memory writes for achieving data consistency can be implemented using the memory fence and the CPU cache line flush instructions, they introduce a significant overhead (more than 10X slower in performance). In this paper, we focus on an important and common data structure, B $_$^+$_$ Tree. Based on our quantitative analysis for consistent tree structures, we propose NV-Tree, a consistent, cache-optimized and workload-adaptive B $_$^+$_$ Tree variant with significantly reduced consistency cost (up to 96 percent reduction in CPU cache line flush). To further optimize NV-Tree under various workloads, we propose a workload-adaptive scheme in which the sizes of individual nodes can be dynamically adjusted to improve the performance over time. We implement and evaluate NV-Tree and NV-Store, a key-value store based on NV-Tree, on an NVDIMM server. NV-Tree outperforms the state-of-art consistent tree structures by up to 12X under write-intensive workloads. NV-Store increases the throughput by up to 7.3X under YCSB workloads compared to Redis.
INDEX TERMS
Nonvolatile memory, Central Processing Unit, Random access memory, Data structures, Phase change materials, Ash, Throughput
CITATION

J. Yang, Q. Wei, C. Wang, C. Chen, K. L. Yong and B. He, "NV-Tree: A Consistent and Workload-Adaptive Tree Structure for Non-Volatile Memory," in IEEE Transactions on Computers, vol. 65, no. 7, pp. 2169-2183, 2016.
doi:10.1109/TC.2015.2479621
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