Issue No. 08 - Aug. (2015 vol. 64)
Qingan Li , State Key Laboratory of Software Engineering and the School of Computer, Wuhan University, Wuhan, China
Yanxiang He , School of Computer, Wuhan University, Wuhan, China
Jianhua Li , School of Computer and Information, Hefei University of Technology, Hefei, China
Liang Shi , School of Computer Science, Chongqing University, Chongqing, China
Yiran Chen , Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburg, PA
Chun Jason Xue , Department of Computer Science, City University of Hong Kong, Hong Kong
Spin-transfer torque RAM (STT-RAM) has been proposed to build on-chip caches because of its attractive features such as high storage density and ultra low leakage power. However, long write latency and high write energy are the two challenges for STT-RAM. Recently, researchers propose to improve the write performance of STT-RAM by relaxing its non-volatility property. To avoid data losses resulting from volatility, refresh schemes have been proposed. However, refresh operations consume additional overhead. In this paper, we propose to significantly reduce the number of refresh operations through re-arranging program data layout at compilation time. An
N-refresh scheme is also proposed to further reduce the number of refreshes. Experimental results show that, on average, the proposed methods can reduce the number of refresh operations by 84.2 percent, and reduce the dynamic energy consumption by 38.0 percent for volatile STT-RAM caches while incurring only 4.1 percent performance degradation.
Equations, Layout, Random access memory, Educational institutions, Resource management, Mathematical model, Silicon
Q. Li, Y. He, J. Li, L. Shi, Y. Chen and C. J. Xue, "Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache," in IEEE Transactions on Computers, vol. 64, no. 8, pp. 2169-2181, 2015.