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Issue No. 06 - June (2015 vol. 64)
ISSN: 0018-9340
pp: 1534-1547
Alberto Ros , Department of Computer Engineering,, Spain
Polychronis Xekalakis , Intel, Santa Clara, CA
Marcelo Cintra , Intel, Santa Clara, CA
Manuel E. Acacio , Department of Computer Engineering,, Spain
Jose M. Garcia , Department of Computer Engineering,, Spain
The design of cache memories is a crucial part of the design cycle of a modern processor, since they are able to bridge the performance gap between the processor and the memory. Unfortunately, caches with low degrees of associativity suffer a large amount of conflict misses. Although by increasing their associativity a significant fraction of these misses can be removed, this comes at a high cost in both power, area, and access time. In this work, we address the problem of high number of conflict misses in low-associative caches, by proposing an indexing policy that adaptively selects the bits from the block address used to index the cache. The basic premise of this work is that the non-uniformity in the set usage is caused by a poor selection of the indexing bits. Instead, by selecting at run time those bits that disperse the working set more evenly across the available sets, a large fraction of the conflict misses (85 percent, on average) can be removed. This leads to IPC improvements of 10.9 percent for the SPEC CPU2006 benchmark suite. By having less accesses in the L2 cache, our proposal also reduces the energy consumption of the cache hierarchy by 13.2 percent. These benefits come with a negligible area overhead.
Indexing, Entropy, Proposals, Correlation, Radiation detectors, Measurement

A. Ros, P. Xekalakis, M. Cintra, M. E. Acacio and J. M. Garcia, "Adaptive Selection of Cache Indexing Bits for Removing Conflict Misses," in IEEE Transactions on Computers, vol. 64, no. 6, pp. 1534-1547, 2015.
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