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Issue No. 12 - Dec. (2013 vol. 62)
ISSN: 0018-9340
pp: 2489-2502
Cristiana Bolchini , Politecnico di Milano, Milano
Antonio Miele , Politecnico di Milano, Milano
This paper proposes a design methodology that enhances the classical system-level design flow for embedded systems to introduce reliability-awareness. The mapping and scheduling step is extended to support the application of hardening techniques to fulfill the required fault management properties that the final system must exhibit; moreover, the methodology allows the designer to specify that only some parts of the systems need to be hardened against faults. The reference architecture is a complex distributed one, constituted by resources with different characteristics in terms of performance and available fault detection/tolerance mechanisms. The approach is evaluated and compared against the most recent and relevant work, with an in-depth analysis on a large set of benchmarks.
Fault tolerance, Fault tolerant systems, Embedded systems, Computer architecture, Event detection, Reliability engineering

C. Bolchini and A. Miele, "Reliability-Driven System-Level Synthesis for Mixed-Critical Embedded Systems," in IEEE Transactions on Computers, vol. 62, no. 12, pp. 2489-2502, 2013.
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