Design of an Energy-Efficient CMOS-Compatible NoC Architecture with Millimeter-Wave Wireless Interconnects
Issue No. 12 - Dec. (2013 vol. 62)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2012.224
Sujay Deb , Indraprastha Institute of Information Technology, Delhi
Kevin Chang , Washington State University, Pullman
Xinmin Yu , Washington State University, Pullman
Suman Prasad Sah , Washington State University, Pullman
Miralem Cosic , Washington State University, Pullman
Amlan Ganguly , Rochester Institute of Technology, Rochester
Partha Pratim Pande , Washington State University, Pullman
Benjamin Belzer , Washington State University, Pullman
Deukhyoun Heo , Washington State University, Pullman
The Network-on-chip (NoC) is an enabling technology to integrate large numbers of embedded cores on a single die. The existing methods of implementing a NoC with planar metal interconnects are deficient due to high latency and significant power consumption arising out of multihop links used in data exchange. To address these problems, we propose design of a hierarchical small-world wireless NoC architecture where the multihop wire interconnects are replaced with high-bandwidth and single-hop long-range wireless shortcuts operating in the millimeter (mm)-wave frequency range. The proposed mm-wave wireless NoC (mWNoC) outperforms the corresponding conventional wireline counterpart in terms of achievable bandwidth and is significantly more energy efficient. The performance improvement is achieved through efficient data routing and optimum placement of wireless hubs. Multiple wireless shortcuts operating simultaneously further enhance the performance, and provide an energy-efficient solution for design of communication infrastructures for multicore chips.
Wireless communication, Computer architecture, Network-on-chip, Performance evaluation, Antennas, System-on-a-chip, Energy efficiency
S. Deb et al., "Design of an Energy-Efficient CMOS-Compatible NoC Architecture with Millimeter-Wave Wireless Interconnects," in IEEE Transactions on Computers, vol. 62, no. 12, pp. 2382-2396, 2013.