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Issue No. 11 - Nov. (2013 vol. 62)
ISSN: 0018-9340
pp: 2238-2251
Jonghun Yoo , Dept. of Electr. & Comput. Eng., Seoul Nat. Univ., Seoul, South Korea
Jaesoo Lee , Dept. of Electr. & Comput. Eng., Seoul Nat. Univ., Seoul, South Korea
Seongsoo Hong , Dept. of Electr. & Comput. Eng., Seoul Nat. Univ., Seoul, South Korea
A flash translation layer (FTL) provides file systems with transparent access to NAND flash memory. Although many applications running on it require real-time guarantees, it is difficult to provide tight worst case execution time (WCET) bounds with conventional static WCET analysis since an FTL exhibits a large variance in execution time depending on its runtime state. Parametric WCET analysis could be an effective alternative but it is also challenging to formulate a parametric WCET function for an FTL program because traditional FTL architecture does not properly model the runtime availability of flash resources in its code structure. To overcome such a limitation, we propose Petri net-based FTL architecture where a Petri net explicitly specifies dependencies between FTL operations and the runtime resource availability. It comes with an FTL operation sequencer that derives at runtime the shortest sequence of FTL operations for servicing an incoming FTL request under the current resource availability. The sequencer computes the WCET of the request by merely summing the WCETs of only those FTL operations in the sequence. Our experimental results show the effectiveness of our FTL architecture. It allowed for tight WCET estimation that yielded WCETs shorter by a factor of 54 than statically analyzed ones.
software architecture, flash memories, logic gates, Petri nets, program diagnostics

Jonghun Yoo, Jaesoo Lee and Seongsoo Hong, "Petri Net-Based FTL Architecture for Parametric WCET Estimation via FTL Operation Sequence Derivation," in IEEE Transactions on Computers, vol. 62, no. 11, pp. 2238-2251, 2013.
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