Subscribe

Issue No.10 - Oct. (2013 vol.62)

pp: 2026-2040

Heng Yu , National University of Singapore, Singapore

Yajun Ha , National University of Singapore, Singapore

Bharadwaj Veeravalli , National University of Singapore, Singapore

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2012.194

ABSTRACT

While quality-adaptable applications are gaining increased popularity on embedded systems (especially multimedia applications), efficient scheduling techniques are necessary to explore this feature to achieve the optimal quality output. In addition to conventional real-time requirements, emerging challenges such as leakage power and multiprocessors further complicate the formulation and solution of adaptive application scheduling problems. In this paper, we propose a dynamic adaptive application scheduling scheme that efficiently distributes the runtime slack to achieve maximized execution quality under timing and dynamic/leakage energy constraints. Our proposed methods are threefold: First, for each task in the slack receiver group, a heuristic guided-search algorithm is proposed to select the optimal processor frequency to maximize the application execution quality. Second, we present an efficient slack receiver selection methodology aiming at identifying optimal slack receivers for quality maximization. Third, our framework is further extended to consider constraints brought by interprocessor communications, where we study the effects of slack inaccuracies introduced by transmission variations, and propose a local scaling approach to compensate the induced quality loss. Experimental results on synthesized tasks and a JPEG2000 codec show that the guided-search algorithm, aided by slack receiver selection, effectively outperforms contemporary approaches with at most 88 percent more quality improvement, whereas the local scaling contributes as large as 16.9 percent on top of the guided-search results.

INDEX TERMS

Receivers, Dynamic scheduling, Heuristic algorithms, Runtime, Processor scheduling, Voltage control, adaptiveness, Embedded multiprocessors, scheduling, quality-of-service

CITATION

Heng Yu, Yajun Ha, Bharadwaj Veeravalli, "Quality-Driven Dynamic Scheduling for Real-Time Adaptive Applications on Multiprocessor Systems",

*IEEE Transactions on Computers*, vol.62, no. 10, pp. 2026-2040, Oct. 2013, doi:10.1109/TC.2012.194REFERENCES

- [1] H. Schwarz, D. Marpe, and T. Wiegand, "Overview of the Scalable Video Coding Extension of the H.264/AVC Standard,"
IEEE Trans. Circuits and Systems for Video Technology, vol. 17, no. 9, pp. 1103-1120, Sept. 2007.- [2] T. Acharya and P.S. Tsai, "JPEG2000 Standard for Image Compression: Concepts,"
Algorithms and VLSI Architectures, Wiley, 2004.- [3] F. Gruian, "System-Level Design Methods for Low-Energy Architectures Containing Variable Voltage Processors,"
Proc. First Int'l Workshop Power-Aware Computer Systems-Revised Papers (PACS '00), pp. 1-12, Nov. 2000.- [4] C. Rusu, R. Melhem, and D. Mosse, "Maximizing Rewards for Real-Time Applications with Energy Constraints,"
ACM Trans. Embedded Computing Systems, vol. 2, no. 4, pp. 537-559, 2003.- [5] L.A. Cortés, P. Eles, and Z. Peng, "Quasi-Static Assignment of Voltages and Optional Cycles in Imprecise-Computation Systems with Energy Considerations,"
IEEE Trans. Very Large Scale Integration Systems, vol. 14, no. 10, pp. 1117-1129, Oct. 2006.- [6] H. Yu, B. Veeravalli, and Y. Ha, "Dynamic Scheduling of Imprecise-Computation Tasks in Maximizing QoS under Energy Constraints for Embedded Systems,"
Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC '08), pp. 452-455, Jan. 2008.- [7] R. Ernst and W. Ye, "Embedded Program Timing Analysis Based on Path Clustering and Architecture Classification,"
Proc. IEEE Int'l Conf. Computer-Aided Design (ICCAD '97), pp. 598-604, 1997.- [8] H. Yu, B. Veeravalli, and Y. Ha, "Leakage-Aware Dynamic Scheduling for Real-Time Adaptive Applications on Multiprocessor Systems,"
Proc. IEEE Design Automation Conf., pp. 493-498, 2010.- [9] D. Zhu, R. Melhem, and B. Childers, "Scheduling with Dynamic Voltage/Speed Adjustment Using Slack Reclamation in Multi-Processor Real-Time Systems,"
IEEE Trans. Parallel and Distributed Systems, vol. 14, no. 7, pp. 686-700, July 2003.- [10] R. Mishra, N. Rastogi, D. Zhu, D. Mosse, and R. Melhem, "Energy Aware Scheduling for Distributed Real-Time Systems,"
Proc. Int'l Parallel and Distributed Processing Symp. (IPDPS '03), 2003.- [11] J.Y. Chung, J.W.S. Liu, and K.J. Lin, "Scheduling Periodic Jobs That Allow Imprecise Results,"
IEEE Trans. Computers, vol. 39, no. 9, pp. 1156-1174, Sept. 1990.- [12] H. Aydin, R. Melhem, D. Mosse, and P. Mejia-Alvarez, "Optimal Reward-Based Scheduling for Periodic Real-Time Tasks,"
IEEE Trans. Computers, vol. 50, no. 2, pp. 111-130, Feb. 2001.- [13] A. Andrei, P. Eles, and Z. Peng, "Energy Optimization of Multiprocessor Systems on Chip by Voltage Selection,"
IEEE Trans. Very Large Scale Integration Systems, vol. 15, no. 3, pp. 262-275, Mar. 2007.- [14] C. Xian, Y.-H. Lu, and Z. Li, "Dynamic Voltage Scaling for Multitasking Real-Time Systems with Uncertain Execution Time,"
IEEE Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 8, pp. 1467-1478, Aug. 2008.- [15] J. Hu and R. Marculescu, "Energy-Aware Communication and Task Scheduling for Network-on-Chip Architectures under Real-Time Constraints,"
Proc. Conf. Design, Automation and Test in Europe (DATE '04), pp. 234-239, 2004.- [16] G. Varatkar and R. Marculescu, "Communication-Aware Task Scheduling and Voltage Selection for Total Systems Energy Minimization,"
Proc. IEEE Int'l Conf. Computer-Aided Design (ICCAD '03), pp. 510-517, 2003.- [17] P. Eles, A. Doboli, P. Pop, and Z. Peng, "Scheduling with Bus Access Optimization for Distributed Embedded Systems,"
IEEE Trans. Very Large Scale Integration Systems, vol. 8, no. 5, pp. 472-491, Oct. 2000.- [18] A. Jantsch and H. Tenhunen,
Networks on Chip. Kluwer Academic, 2003.- [19] Z. Lu and A. Jantsch, "Slot Allocation for TDM Virtual-Circuit Configuration for Network-on-Chip,"
Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD '07), pp. 18-25, 2007.- [20] K. Goossens, J. Dielissen, and A. Radulescu, "Æthereal Network on Chip: Concepts, Architectures and Implementations,"
IEEE Design and Test, vol. 22, no. 5, pp. 414-421, Sept. 2005.- [21] M. Millberg, E. Nilsson, R. Thid, and A. Jantsch, "Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network-on-Chip,"
Proc. Conf. Design, Automation and Test in Europe (DATE '04), pp. 890-895, 2004.- [22] J. Duato, S. Yalamanchili, and L.M. Ni,
Interconnection Networks: An Engineering Approach. Morgan Kaufmann, 2003.- [23] G.-M. Chiu, "The Odd-Even Turn Model for Adaptive Routing,"
IEEE Trans. Parallel and Distributed Systems, vol. 11, no. 7, pp. 729-738, July 2000.- [24] J. Hu and R. Marculescu, "DyAD: Smart Routing for Networks-on-Chip,"
Proc. 41st Ann. Design Automation Conf. (DAC '04), pp. 260-263, 2004.- [25] M.H. Cho et al., "Path-Based, Randomized, Oblivious, Minimal Routing,"
Proc. Int'l Workshop Network on Chip Architecture, pp. 23-28, 2009.- [26] E. Bolotin, I. Cidon, R. Ginosaur, and A. Kolodny, "QNoC: QoS Architecture and Design Process for Network-on-Chip,"
J. Systems Architecture, vol. 50, nos. 2/3, pp. 105-128, 2004.- [27] D. Andreasson and S. Kumar, "Slack-Time Aware Routing in NoC Systems,"
Proc. Int'l Symp. Circuits and Systems (ISCAS '05), pp. 2353-2356, 2005.- [28] E. Beigne et al., "An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework,"
Proc. Int'l Symp. Asynchronous Circuits and Systems (ASYNC '05), pp. 54-63, 2005.- [29] S.M. Martin, K. Flautner, T. Mudge, and D. Blaauw, "Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Low Power Micropossers Under Dynamic Work Loads,"
Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD '02), pp. 721-725, 2002.- [30] T.F. Abdelzaher, E.M. Atkins, and K.-G. Shin, "QoS Negotiation in Real-Time Systems and Its Application to Automated Flight Control,"
IEEE Trans. Computers, vol. 49, no. 11, pp. 1170-1183, Nov. 2000.- [31] R.M. Karp, R.E. Miller, and J.W. Thatcher, "Reducibility Among Combinatorial Problems,"
J. Symbolic Logic, vol. 40, no. 4, pp. 618-619, 1975.- [32] A. Björklund, T. Husfeldt, and M. Koivisto, "Set Partitioning via Inclusion-Exclusion,"
SIAM J. Computing, vol. 39, no. 2, pp. 546-563, 2009.- [33] "SESC: Cycle Accurate Architectural Simulator," http:/sesc. sourceforge.net, 2013.
- [34] "NIRGAM: A Simulator for NoC Interconnect Routing and Application Modeling," http:/www.nirgam.ecs.soton.ac.uk, 2013.
- [35] L.M. Ni and P.K. McKinley, "A Survey of Wormhole Routing Techniques in Direct Networks,"
Computer, vol. 26, no. 2, pp. 62-76, Feb. 1993.- [36] R.P. Dick, D.L. Rhodes, and W. Wolf, "TGFF: Task Graphs for Free,"
Proc. Sixth Int'l Workshop Hardware/Software Codesign (CODES '98), pp. 97-101, 1998. |