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Issue No.09 - Sept. (2013 vol.62)

pp: 1694-1704

Jinghang Liang , University of Alberta, Edmonton

Jie Han , University of Alberta, Edmonton

Fabrizio Lombardi , Notheastern University, Boston

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2012.147

ABSTRACT

Scaling of CMOS technology into nanometric feature sizes has raised concerns for the reliable operation of logic circuits, such as in the presence of soft errors. This paper deals with the analysis of the operation of sequential circuits. As the feedback signals in a sequential circuit can be logically masked by specific combinations of primary inputs, the cumulative effects of soft errors can be eliminated. This phenomenon, referred to as error masking, is related to the presence of so-called restoring inputs and/or the consecutive presence of specific inputs in multiple clock cycles (equivalent to a synchronizing sequence in switching theory). In this paper, error masking is extensively analyzed using the operations of state transition matrices (STMs) and binary decision diagrams (BDDs) of a finite state machine (FSM) model. The characteristics of state transitions with respect to correlations between the restoring inputs and time sequence are mathematically established using STMs; although the applicability of the STM analysis is restricted due to its complexity, the BDD approach is more efficient and scalable for use in the analysis of large circuits. These results are supported by simulations of benchmark circuits and may provide a basis for further devising efficient and robust implementations when designing FSMs.

INDEX TERMS

Sequential circuits, Integrated circuit reliability, Data structures, Boolean functions, Integrated circuit modeling, Probabilistic logic, soft errors, Finite state machines (FSMs), error masking, sequential circuits, state transition matrices (STMs), transition probability matrices, binary decision diagrams (BDDs)

CITATION

Jinghang Liang, Jie Han, Fabrizio Lombardi, "Analysis of Error Masking and Restoring Properties of Sequential Circuits",

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