Pages: pp. 1478-1480
Modern computer systems face increasing demands for high performance, programmability, and low power under tight time-to-market, budget and reliability constraints. Because of the conflicting nature of many of these requirements, adaptive systems are being put forward as efficacious and efficient solutions for many applications whereby the same system can be harnessed to meet time-varying requirements and constraints, including speed performance, power consumption, and quality of service.
This special section of IEEE Transactions on Computers presents some of the latest research developments in the field of adaptive hardware and systems. The creation of this section was motivated by lively discussions held at the annual NASA/ESA Adaptive Hardware and Systems (AHS) conference, which showed a need for such special section at a top ranked journal. At the end of a rigorous review process, ten papers were selected for publication from a set of high quality submissions consisting of regular papers and extended papers from the AHS 2012 conference proceedings ( http://www.see.ed.ac.uk/ahs2012/).
The first article, “Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing,” by Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, and Lukas Sekanina, presents an FPGA-based self-evolvable hardware system that can generate digital circuits autonomously using a set of basic processing elements that can be reconfigured on the fly using FPGAs' partial dynamic reconfiguration feature. The system is demonstrated using digital image filtering and edge detection applications showing better adaptation to different noise types and intensities compared to classical approaches, as well as nondegrading filtering behavior.
The second article, “Test Strategies for Reliable Runtime Reconfigurable Architectures,” by Lars Bauer, Claus Braun, Michael E. Imhof, Michael A. Kochte, Eric Schneider, Hongyan Zhang, Jörg Henkel, and Hans-Joachim Wunderlich, deals with the issue of reliable reconfigurable computing by proposing two nonconcurrent runtime test strategies: 1) Preconfiguration online tests (PRET) for testing hardware structures e.g. partial reconfiguration region containers, and 2) Post-configuration online tests (PORT) for testing accelerators that are dynamically configured into the chip at runtime. The paper discusses system integration issues including test scheduling and resource management, and shows how these can be used to achieve high fault coverage and low test latency at low performance penalty.
The third article, “A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing,” by Luca Sterpone, Mario Porrmann, and Jens Hagemeyer, presents an FPGA-based scalable prototyping platform for fault-tolerant processing systems of satellite payload. An analysis of radiation effects on the most critical components of the platform led to the development of an adaptive mapping algorithm which reduces the erroneous effects of emerging faults.
The fourth article, “Scalable FPGA Refurbishment Using Netlist-Driven Evolutionary Algorithms,” by Rizwan Arshad Ashraf and Ronald F. DeMara, presents a novel evolutionary technique which allows for the autonomous runtime recovery from faults in mission critical applications. The technique exploits design-time circuit netlist information to drastically reduce the search space of evolvable hardware and uses partial dynamic reconfiguration to evolve circuits over time.
The fifth article, “R3TOS: A Novel Reliable Reconfigurable Real-Time Operating System for Highly Adaptive, Efficient, and Dependable Computing on FPGAs,” by Xabier Iturbe, Khaled Benkrid, Chuan Hong, Ali Ebrahim, Raul Torrego, Imanol Martinez, Tughrul Arslan, and Jon Perez, attempts to tackle the problem of reliable, fault-tolerant and real-time reconfigurable computing through the systematic development of software operating system for FPGAs. The paper presents the various components of R3TOS including hardware task placers and schedulers, and the programmer's API. A proof-of-concept implementation based on Virtex-4 FPGAs is also presented.
The sixth article, “Novel Techniques for Smart Adaptive Multiprocessor SoCs,” by Luciano Ost, Garibotti, Gilles Sassatelli, Gabriel Marchesan Almeida, Rémi Busseuil, Anastasiia Butko, Michel Robert, and Jürgen Becker, presents a scalable distributed homogeneous multiprocessor system aimed at adaptive high-performance efficient multiprocessing. The architecture allows for local distributed control with processor-level frequency scaling, task migration for load balancing, message passing between tasks, and distributed shared-memory multithreading.
The seventh article, “A Cache Tuning Heuristic for Multicore Architectures,” by Marisha Rawlins and Ann Gordon-Ross, presents cache-tuning heuristics for multicore architectures which considerably reduce energy consumption. For instance, by classifying applications based on data sharing and cache behavior, a proposed level-one data cache tuning heuristic reduces the design space search to 1 percent and achieves 25 percent energy savings in the data cache subsystem. This shows the advantage of adapting cache architecture to the application in hand.
The eighth article, “PAnDA: A Reconfigurable Architecture that Adapts to Physical Substrate Variations,” by James Alfred Walker, Martin A. Trefzer, Simon J. Bale, and Andy M. Tyrrell, presents a hierarchical architecture (PaNDA) which can be seen as a traditional FPGA at the top level, while at the bottom level the architecture consists of an array of transistors which can be configured in different ways to compensate for intrinsic stochastic variability. In between the two layers lie configurable analogue blocks, which can be tuned to provide adaptation to stochastic variability, improve chip performance, and/or even recover from faults.
The ninth article, “Memristor-Based Neural Logic Blocks for Nonlinearly Separable Functions,” by Michael Soltiz, Dhireesha Kudithipudi, Cory Merkel, Garrett S. Rose, and Robinson E. Pino, presents memristor-based adaptive neural logic blocks for biologically-inspired reconfigurable hardware systems. The proposed neural logic blocks can adapt the effective activation function during the training process hence reducing the resource requirement of the underlying system and improving its performance. Experimental results for ISCAS-85 benchmark circuits and OCR application support the efficacy and efficiency claims of the proposed solution.
The tenth and final article of this special section, “Optimization of Weighted Finite State Transducer for Speech Recognition,” by Louis-Marie Aubert, Roger Woods, Scott Fischaber, and Richard Veitch, presents a modified adaptive weighted finite state transducer (WFST) which drastically reduces memory access requirement in speech recognition applications with a small loss of accuracy. The proposed WSTF is aimed at embedded speech recognition hardware.
We hope that the readership will find the above selection of papers both useful and stimulating.
We finally take this opportunity to thank the contributing authors, reviewers, the editorial staff for IEEE TC, and the Editor-in-Chief, Professor Albert Zomaya, for their hard work and professionalism. Without their support, this special section would not have been possible.
Umeshkumar D. Patel