Issue No. 05 - May (2013 vol. 62)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2012.42
Rafael Ubal , Northeastern University, Boston
Julio Sahuquillo , University Politecnica de Valencia, Valencia
Salvador Petit , University Politecnica de Valencia, Valencia
Pedro Lopez , University Politecnica de Valencia, Valencia
Jose Duato , Technical University of Valencia, Valencia
Multicore chips are currently dominating the microprocessor market as designs that improve performance and sustain power consumption. However, complex core features must be still considered to provide good performance for existing sequential applications. An effective approach to reduce core complexity without dramatically sacrificing performance is to distribute critical processor structures by using clustered microarchitectures. In these designs, communication latency among clusters is a critical performance bottleneck, and a good steering algorithm is required to reduce intercluster communication. In this paper, we propose a new energy-efficient microarchitectural approach that reduces intercluster communication by detecting and generating independent chains of instructions, referred to as subtraces, from the execution of sequential programs. The devised mechanism has been modeled on an x86-based trace-cache processor, where subtraces are built in the fill unit, stored in a trace cache, and individually steered to different clusters. Experimental results show that the proposal reaches performance speedups around 7 and 15 percent for point-to-point and bus-based interconnects, respectively, while achieving energy savings of up to 12 percent.
cache storage, computational complexity, microprocessor chips, multiprocessing systems, parallel architectures, performance evaluation, power consumption
R. Ubal, J. Sahuquillo, S. Petit, P. Lopez and J. Duato, "Hardware-based generation of independent subtraces of instructions in clustered processors," in IEEE Transactions on Computers, vol. 62, no. 5, pp. 944-955, 2013.