Issue No. 04 - April (2013 vol. 62)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2012.34
A. Morari , Pacific Northwest Nat. Lab., Richland, WA, USA
C. Boneti , Schlumberger Brazil Res. & Geoengineering Center (BRGC), Houston, TX, USA
F. J. Cazorla , Barcelona Supercomput. Center, Barcelona, Spain
R. Gioiosa , Barcelona Supercomput. Center, Barcelona, Spain
Chen-Yong Cher , Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
A. Buyuktosunoglu , Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
P. Bose , Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
M. Valero , Barcelona Supercomput. Center, Barcelona, Spain
While several hardware mechanisms have been proposed to control the interaction between hardware threads in an SMT processor, few have addressed the issue of software-controllable SMT performance. The IBM POWER5 and POWER6 are the first high-performance processors implementing a software-controllable hardware-thread prioritization mechanism that controls the rate at which each hardware-thread decodes instructions. This paper shows the potential of this basic mechanism to improve several target metrics for various applications on POWER5 and POWER6 processors. Our results show that although the software interface is exactly the same, the software-controlled priority mechanism has a different effect on POWER5 and POWER6. For instance, hardware threads in POWER6 are less sensitive to priorities than in POWER5 due to the in order design. We study the SMT thread malleability to enable user-level optimizations that leverage software-controlled thread priorities. We also show how to achieve various system objectives such as parallel application load balancing, in order to reduce execution time. Finally, we characterize user-level transparent execution on POWER5 and POWER6, and identify the workload mix that best benefits from it.
resource allocation, microprocessor chips, multi-threading, simultaneous multithreading, SMT malleability, IBM POWER5 processor, IBM POWER6 processor, hardware mechanism, hardware thread, software-controllable SMT performance, SMT processor, software-controllable hardware-thread prioritization mechanism, software interface, software-controlled priority mechanism, user-level optimization, parallel application load balancing, execution time, user-level transparent execution, Instruction sets, Hardware, Benchmark testing, Kernel, Linux, IBM POWER6, Malleability, simultaneous multithreading, hardware-thread priorities, IBM POWER5
P. Bose et al., "SMT Malleability in IBM POWER5 and POWER6 Processors," in IEEE Transactions on Computers, vol. 62, no. , pp. 813-826, 2013.