The Community for Technology Leaders
RSS Icon
Issue No.04 - April (2013 vol.62)
pp: 730-743
Sourav Sen Gupta , Indian Stat. Inst., ASU, Kolkata, India
A. Chattopadhyay , UMIC Res. Centre, RWTH Aachen Univ., Aachen, Germany
K. Sinha , Hewlett Packard Labs., Bangalore, India
S. Maitra , Indian Stat. Inst., ASU, Kolkata, India
B. P. Sinha , Indian Stat. Inst., ACMU, Kolkata, India
RC4 is the most popular stream cipher in the domain of cryptology. In this paper, we present a systematic study of the hardware implementation of RC4, and propose the fastest known architecture for the cipher. We combine the ideas of hardware pipeline and loop unrolling to design an architecture that produces 2 RC4 keystream bytes per clock cycle. We have optimized and implemented our proposed design using VHDL description, synthesized with 130, 90, and 65 nm fabrication technologies at clock frequencies 625 MHz, 1.37 GHz, and 1.92 GHz, respectively, to obtain a final RC4 keystream throughput of 10, 21.92, and 30.72 Gbps in the respective technologies.
hardware description languages, cryptography, frequency 1.92 GHz, RC4 stream cipher, cryptology domain, VHDL description, Verilog high scale description language, RC4 keystream throughput, size 130 nm, size 90 nm, size 65 nm, frequency 625 MHz, frequency 1.37 GHz, Hardware, Registers, Throughput, Adders, Clocks, Pipeline processing, Computer architecture, stream cipher, Cryptography, hardware accelerator, high throughput, loop unrolling, pipelining, RC4
Sourav Sen Gupta, A. Chattopadhyay, K. Sinha, S. Maitra, B. P. Sinha, "High-Performance Hardware Implementation for RC4 Stream Cipher", IEEE Transactions on Computers, vol.62, no. 4, pp. 730-743, April 2013, doi:10.1109/TC.2012.19
[1] Software Performance Results from the eSTREAM Project, eSTREAM, the ECRYPT Stream Cipher Project, http://www. , 2012.
[2] The Current eSTREAM Portfolio, eSTREAM, the ECRYPT Stream Cipher Project, , 2012.
[3] S.R. Fluhrer and D.A. McGrew, "Statistical Analysis of the Alleged RC4 Keystream Generator," Proc. Seventh Int'l Workshop Fast Software Encryption (FSE '00), vol. 1978, pp. 19-30, 2000.
[4] S.R. Fluhrer, I. Mantin, and A. Shamir, "Weaknesses in the Key Scheduling Algorithm of RC4," Proc. Eighth Ann. Int'l Workshop Selected Areas in Cryptography (SAC '01), vol. 2259, pp. 1-24, 2001.
[5] M.D. Galanis, P. Kitsos, G. Kostopoulos, N. Sklavos, and C.E. Goutis, "Comparison of the Hardware Implementation of Stream Ciphers," Int'l Arab J. Information Technology, vol. 2, no. 4, pp. 267-274, 2005.
[6] J. Golic, "Linear Statistical Weakness of Alleged RC4 Keystream Generator," Proc. Advances in Cryptology EUROCRYPT, vol. 1233, pp. 226-238, 1997.
[7] T. Good and M. Benaissa, "Hardware Results for Selected Stream Cipher Candidates," eSTREAM, ECRYPT Stream Cipher Project, SASC, Report 2007/023, 2007.
[8] F.K. Gurkaynak, P. Luethi, N. Bernold, R. Blattmann, V. Goode, M. Marghitola, H. Kaeslin, N. Felber, and W. Fichtner, "Hardware Evaluation of eSTREAM Candidates: Achterbahn, Grain, MICKEY, MOSQUITO, SFINKS, Trivium, VEST, ZK-Crypt," eSTREAM, ECRYPT Stream Cipher Project, Report 2006/015, 2006.
[9] P. Hamalainen, M. Hannikainen, T. Hamalainen, and J. Saarinen, "Hardware Implementation of the Improved WEP and RC4 Encryption Algorithms for Wireless Terminals," Proc. European Signal Processing Conf., pp. 2289-2292, 2000.
[10] P. Kitsos, G. Kostopoulos, N. Sklavos, and O. Koufopavlou, "Hardware Implementation of the RC4 Stream Cipher," Proc. IEEE 46th Midwest Symp. Circuits and Systems, Kitsos_c14.pdf, 2003.
[11] J.-D. Lee and C.-P. Fan, "Efficient Low-Latency RC4 Architecture Designs for IEEE 802.11i WEP/TKIP," Proc. Int'l Symp. Intelligent Signal Processing and Comm. Systems (ISPACS '07), pp. 56-59, 2007.
[12] T. Lynch and E.E. SwartzlanderJr., "A Spanning Tree Carry Lookahead Adder," IEEE Trans. Computers, vol. 41, no. 8, pp. 931-939, Aug. 1992.
[13] I. Mantin, "Predicting and Distinguishing Attacks on RC4 Keystream Generator," Proc. 24th Ann. Int'l Conf. Theory and Applications of Cryptographic Techniques (EUROCRYPT '05), vol. 3494, pp. 491-506, 2005.
[14] I. Mantin, "A Practical Attack on the Fixed RC4 in the WEP Mode," Proc. 11th Int'l Conf. Theory and Application of Cryptology and Information Security, vol. 3788, pp. 395-411, 2005.
[15] I. Mantin and A. Shamir, "A Practical Attack on Broadcast RC4," Proc. Eighth Int'l Workshop Fast Software Encryption (FSE '01), vol. 2355, pp. 152-164, 2001.
[16] D.P. MatthewsJr., "System and Method for a Fast Hardware Implementation of RC4," US Patent Number 6549622, Campbell, CA, http://www.freepatentsonline.com6549622.html , Apr. 2003.
[17] D.P. MatthewsJr., "Methods and Apparatus for Accelerating ARC4 Processing," US Patent Number 7403615, Morgan Hill, CA, http://www.freepatentsonline.com7403615.html , July 2008.
[18] A. Maximov and D. Khovratovich, "New State Recovering Attack on RC4," Proc. 28th Ann. Conf. Cryptology: Advances in Cryptology, vol. 5157, pp. 297-316, 2008.
[19] I. Mironov, "(Not So) Random Shuffles of RC4," Proc. 22nd Ann. Int'l Cryptology Conf. Advances in Cryptology, pp. 304-319, 2002.
[20] G. Paul and S. Maitra, "On Biases of Permutation and Keystream Bytes of RC4 Towards the Secret Key," Cryptography and Comm., vol. 1, no. 2, pp. 225-268, 2009.
[21] A. Roos, "A Class of Weak Keys in the RC4 Stream Cipher," Two Posts in sci.crypt,, 1995.
[22] S. Sen Gupta, K. Sinha, S. Maitra, and B.P. Sinha, "One Byte per Clock: A Novel RC4 Hardware," Proc. INDOCRYPT '10, vol. 6498, pp. 347-363, 2010.
[23] B.P. Sinha and P.K. Srimani, "Fast Parallel Algorithms for Binary Multiplication and Their Implementation on Systolic Architectures," IEEE Trans. Computers, vol. 38, no. 3, pp. 424-431, Mar. 1989.
[24] D. Wagner My RC4 Weak Keys, Post in sci.crypt, , 1995.
3 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool