Issue No. 04 - April (2013 vol. 62)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2012.32
C. Ttofis , Dept. of Electr. & Comput. Eng., Univ. of Cyprus, Nicosia, Cyprus
S. Hadjitheophanous , Dept. of Electr. & Comput. Eng., Univ. of Cyprus, Nicosia, Cyprus
A. S. Georghiades , Dept. of Electr. & Comput. Eng., Univ. of Cyprus, Nicosia, Cyprus
T. Theocharides , Dept. of Electr. & Comput. Eng., Univ. of Cyprus, Nicosia, Cyprus
Stereo Vision, a technique aimed at inferring depth information from stereo images, has been used in a wide range of computer vision applications, with real-time requirements in emerging embedded vision systems. Computation of the disparity map, a vital step in extracting depth information from stereo images, requires a significant amount of computational resources. As such, existing software implementations require high-end hardware platforms to achieve real-time frame rates, suggesting that dedicated hardware mechanisms might be more suitable for embedded applications. In this paper, we present a disparity map computation architecture targeting embedded stereo vision applications with hard real-time requirements. The architecture integrates a hardware edge detection mechanism that reduces the search space, improving the overall performance, and is configurable in terms of various application parameters, making it suitable for a number of application environments. The paper also presents a study on the impact of the various parameters in terms of the performance and hardware/power overheads. An experimental prototype of the architecture was implemented on the Xilinx ML505 FPGA Evaluation Platform, achieving 50 Frames Per Second (fps) for 1,280 × 1,024 image sizes. Moreover, the quality of the disparity maps generated by the proposed system is comparable to other existing hardware implementations featuring local stereo correspondence methods.
stereo image processing, computer vision, edge detection, feature extraction, field programmable gate arrays, local stereo correspondence method, edge-directed hardware architecture, realtime disparity map computation, stereo image, depth information extraction, embedded vision system, embedded stereo vision application, hardware edge detection mechanism, application parameter, hardware-power overhead, performance overhead, ML505 FPGA evaluation platform, field programmable gate array, image size, Image edge detection, Hardware, Computer architecture, Stereo vision, Real time systems, Correlation, Detectors, image processing, Stereo vision systems, real-time disparity map computation, FPGA design
S. Hadjitheophanous, C. Ttofis, A. S. Georghiades and T. Theocharides, "Edge-Directed Hardware Architecture for Real-Time Disparity Map Computation," in IEEE Transactions on Computers, vol. 62, no. , pp. 690-704, 2013.