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Issue No.01 - Jan. (2013 vol.62)
pp: 45-58
Emiliano Betti , University of Illinois at Urbana-Champaign, Urbana
Stanley Bak , University of Illinois at Urbana-Champaign, Urbana
Rodolfo Pellizzoni , University of Waterloo, Waterloo
Marco Caccamo , University of Illinois at Urbana-Champaign, Urbana
Lui Sha , University of Illinois at Urbana-Champaign, Urbana
Real-time embedded systems are increasingly being built using commercial-off-the-shelf (COTS) components such as mass-produced peripherals and buses to reduce costs, time-to-market, and increase performance. Unfortunately, COTS-interconnect systems do not usually guarantee timeliness, and might experience severe timing degradation in the presence of high-bandwidth I/O peripherals. Moreover, peripherals do not implement any internal priority-based scheduling mechanism, hence, sharing a device can result in data of high priority tasks being delayed by data of low priority tasks. To address these problems, we designed a real-time I/O management system comprised of 1) real-time bridges with I/O virtualization capabilities, and 2) a peripheral scheduler. The proposed framework is used to transparently put the I/O subsystem of a COTS-based embedded system under the discipline of real-time scheduling, minimizing the timing unpredictability due to the peripherals sharing the bus. We also discuss computing the maximum delay due to buffered I/O data transactions as well as determining the buffer size needed to avoid data loss. Finally, we demonstrate experimentally that our prototype real-time I/O management system successfully exports multiple virtual devices for a single physical device and prioritizes I/O traffic, guaranteeing its timeliness.
Real time systems, Servers, Processor scheduling, Bridges, Scheduling, Hardware, Delay, COTS, Real-time, Linux, input/output, peripheral, bus, scheduling
Emiliano Betti, Stanley Bak, Rodolfo Pellizzoni, Marco Caccamo, Lui Sha, "Real-Time I/O Management System with COTS Peripherals", IEEE Transactions on Computers, vol.62, no. 1, pp. 45-58, Jan. 2013, doi:10.1109/TC.2011.202
[1] PCISIG, “Conventional pci 3.0, pci-x 2.0 and pci-e 2.0 Specifications,”, 2009.
[2] K. Hoyme and K. Driscoll, “SAFEbus,” IEEE Aerospace Electronic Systems Magazine, vol. 8, no. 3, pp. 34-39, Mar. 1993.
[3] J. Pike, “Hh-60g Pave Hawk,” aircrafthh-60g.htm, 2009.
[4] M. Alvarez, E. Salami, A. Ramirez, and M. Valero, “A Performance Characterization of High Definition Digital Video Decoding Using h.264/avc,” Proc. IEEE Int'l Workload Characterization Symp., Oct. 2005.
[5] M.Y. Nam, R. Pellizzoni, R.M. Bradford, and L. Sha, “ASIIST: Application Specic I/O Integration Support Tool for Real-Time Bus Architecture Designs,” Proc. IEEE 14th Int'l Conf. Eng. of Complex Computer Systems (ICECCS), 2009.
[6] J.-Y.L. Boudec and P. Thiran, Network Calculus: A Theory of Deterministic Queuing Systems for the Internet. Springer, 2001.
[7] S. Bak, E. Betti, R. Pellizzoni, M. Caccamo, and L. Sha, “Real-Time Control of i/o Cots Peripherals for Embedded Systems,” Proc. IEEE 30th Real-Time Systems Symp., Dec. 2009.
[8] R. Pellizzoni, B. Bui, M. Caccamo, and L. Sha, “Coscheduling of CPU and I/O Transactions in COTS-Based Embedded Systems,” Proc. Real-Time Systems Symp., pp. 221-231, Dec. 2008.
[9] R. Pellizzoni and M. Caccamo, “Impact of Peripheral-Processor Interference on Wcet Analysis of Real-Time Embedded Systems,” IEEE Trans. Computers, vol. 59, no. 3, pp. 400-415, Mar. 2010.
[10] S. Schönberg, “Impact of pci-Bus Load on Applications in a pc Architecture,” Proc. IEEE 24th Int'l Real-Time Systems Symp., Dec. 2003.
[11] T.-Y. Huang, J.W.S. Liu, and J.-Y. Chung, “Allowing Cycle-Stealing Direct Memory Access i/o Concurrent with Hard-Real-Time Programs,” Proc. Int'l Conf. Parallel and Distributed Systems, 1996.
[12] J. Rosen, P.E.A. Andrei, and Z. Peng, “Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip,” Proc. IEEE 28th Real-Time System Symp., Dec. 2007.
[13] S. Chattopadhyay, A. Roychoudhury, and T. Mitra, “Modeling Shared Cache and Bus in Multi-Cores for Timing Analysis,” Proc. Software and Compilers for Embedded Systems, 2010.
[14] S. Schliecker, M. Negrean, G. Nicolescu, P. Paulin, and R. Ernst, “Reliable Performance Analysis of a Multicore Multithreaded System-on-Chip,” Proc. IEEE/ACM/IFIP Sixth Int'l Conf. Hardware/Software Codesign and System Synthesis (CODES$+$ ISSS), Oct. 2008.
[15] L. Thiele, S. Chakraborty, and M. Naedele, “Real-Time Calculus for Scheduling Hard Real-Time Systems,” Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS), 2000.
[16] E. Wandeler, L. Thiele, M. Verhoef, and P. Lieverse, “System Architecture Evaluation Using Modular Performance Analysis: A Case Study,” Int'l J. Software Tools for Technology Transfer, vol. 9, no. 6, pp. 649-667, Nov. 2006.
[17] K.W. Tindell, H. Hansson, and A.J. Wellings, “Analysing Real-Time Communication: Controller Area Network (CAN),” Proc. IEEE Real-Time Systems Symp., Dec. 1994.
[18] B. Zhang, X. Wang, R. Lai, L. Yang, Y. Luo, X. Li, and Z. Wang, “A Survey on i/o Virtualization and Optimization,” Proc. Fifth Ann. ChinaGrid Conf. (ChinaGrid), pp. 117-123, July 2010.
[19] PCISIG, “Single Root i/o Virtualization and Sharing 1.1 Specification,” single_root, 2010.
[20] S. Chinni and R. Hiremane, “Virtual Machine Device Queues,” Intel, whitepaper, 2007.
[21] I. Corporation, “Achieving Fast, Scalable i/o for Virtualized Servers,” products/whitepapers322680.pdf, 2009.
[22] I. Corporation, “Intel 82599 10 Gigabit Ethernet Controller,” prodbrf321731. pdf, 2011.
[23] C.L. Liu and J.W. Layland, “Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment,” J. ACM, vol. 20, no. 1, pp. 46-61, 1973.
[24] G. Buttazzo, Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications, second ed. Kluwer Academic Publishers, 2004.
[25] L.S.B. Sprunt and J.P. Lehoczky, “Scheduling Sporadic and Aperiodic Events in a Hard Real-Time System,” technical report, CMU, 1989.
[26] M. Spuri and G. Buttazzo, “Efficient Aperiodic Service Under Earliest Deadline Scheduling,” Proc. Real-Time Systems Symp., pp. 2-11, Dec. 1994.
[27] R. Pellizzoni, E. Betti, S. Bak, G. Yao, J. Criswell, M. Caccamo, and R. Kegley, “A Predictable Execution Model for Cots-Based Embedded Systems,” Proc. 17th Real-Time and Embedded Technology and Applications Symp., Apr. 2011.
[28] Xilinx, “Virtex-5 LXT FPGA ML505 Evaluation Platform,” , 2008.
[29] B. Sprunt, L. Sha, and J. Lehoczky, “Aperiodic Task Scheduling for Hard-Real-Time Systems,” J. Real-Time Systems, vol. 1, pp. 27-60. July 1989.
[30] Xilinx, “Ml455,” documentation ml455.htm, 2009.
[31] Xilinx, “Ml507,” , 2009.
[32] Xilinx, “Microblaze Soft Processor Core,”, 2009.
[33] J. Lehoczky, L. Sha, and Y. Ding, “The Rate Monotonic Scheduling Algorithm: Exact Characterization and Average Case Behavior,” Proc. IEEE Real-Time Systems Symp., Dec. 1989.
[34] M. Spuri, “Analysis of Deadline Scheduled Real-Time Systems,” Technical Report RR-2772, INRIA, France, Jan. 1996.
[35] S. Chakraborty, S. Kunzli, and L. Thiele, “A General Framework for Analysing System Properties in Platform-Based Embedded System Design,” Proc. Sixth Design, Automation and Test in Europe (DATE), 2003.
[36] Xilinx, “Virtex-5 LXT ML555 FPGA Development Kit for PCI Express, PCI-X, and PCI Interfaces,” , 2009.
[37] M. Marinoni, T. Facchinetti, G. Buttazzo, and G. Franchino, “An Embedded Real-Time System for Autonomous Flight Control,” Proc. 50th Int'l Congress ANIPLA on Methodologies for Emerging Technologies in Automation, 2006.
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