Issue No. 09 - Sept. (2012 vol. 61)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2011.153
Miaoqing Huang , University of Arkansas, Fayetteville
Vikram K. Narayana , The George Washington University, Washington DC
Mohamed Bakhouya , Technical University of Belfort Montbeliard, Cedex
Jaafar Gaber , Technical University of Belfort Montbeliard, Cedex
Tarek El-Ghazawi , The George Washington University, Washington DC
High-performance reconfigurable computing involves acceleration of significant portions of an application using reconfigurable hardware. Mapping application task graphs onto reconfigurable hardware is, therefore, of rising attention. In this work, we approach the mapping problem by incorporating multiple architectural variants for each hardware task; the variants reflect tradeoffs between the logic resources consumed and the task execution throughput. We propose a mapping approach based on the genetic algorithm, and show its effectiveness for random task graphs as well as an N-body simulation application, demonstrating improvements of up to 78.6 percent in the execution time compared with choosing a fixed implementation variant for all tasks. We then validate our methodology through experiments on real hardware, an SRC-6 reconfigurable computer.
Hardware task mapping, genetic algorithm, reconfigurable computing.
M. Huang, V. K. Narayana, M. Bakhouya, J. Gaber and T. El-Ghazawi, "Efficient Mapping of Task Graphs onto Reconfigurable Hardware Using Architectural Variants," in IEEE Transactions on Computers, vol. 61, no. , pp. 1354-1360, 2011.