The Community for Technology Leaders
RSS Icon
Issue No.09 - Sept. (2012 vol.61)
pp: 1311-1324
B. D. Bui , Comput. Sci. Dept., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
R. Pellizzoni , Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada
M. Caccamo , Comput. Sci. Dept., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
We address the problem of scheduling concurrent periodic real-time transactions on Multidomain Ring Bus (MDRB). The problem is challenging because although the bus allows multiple nonoverlapping transactions to be executed concurrently, the degree of concurrency depends on the topology of the bus and of executed transactions. To solve this problem, first, we propose two novel efficient scheduling algorithms for topographically acyclic transaction sets. The first algorithm is optimal for transaction sets under restrictive assumptions while the second one induces a good sufficient schedulable utilization bound for more general transaction sets. Then, we extend these two algorithms for the scheduling of topographically cyclic transaction sets. Extensive simulations show that the proposed algorithm can schedule transaction sets with high bus utilization and is better than that of related works in most practical settings. The implementation of the algorithms in a real testbed shows that they have relatively low execution-time overhead.
system buses, multiprocessing systems, network topology, network-on-chip, processor scheduling, SoC, concurrent periodic real-time transaction scheduling, multidomain ring buses, MDRB, multiple nonoverlapping transactions, bus topology, topographical acyclic transaction sets, execution-time overhead, real-time network-on-chip scheduling, NoC, many-core system-on-chip, Real time systems, Schedules, System-on-a-chip, Scheduling, Optimal scheduling, Scheduling algorithm, real-time network-on-chip scheduling., Real-time communications, real-time scheduling
B. D. Bui, R. Pellizzoni, M. Caccamo, "Real-Time Scheduling of Concurrent Transactions in Multidomain Ring Buses", IEEE Transactions on Computers, vol.61, no. 9, pp. 1311-1324, Sept. 2012, doi:10.1109/TC.2011.151
[1] A. Agarwal, C. Iskander, and R. Shankar, “Survey of Network-on-Chip (NoC) Architectures & Contributions,” J. Eng., Computing and Architecture, vol. 3, no. 1, 2009.
[2] T.W. Ainsworth and T.M. Pinkston, “Characterizing the Cell EIB On-Chip Network,” IEEE Micro, vol. 27, no. 5, pp. 6-14, Sept./Oct. 2007.
[3] S. Balakrishnan and F. Özgüner, “A Priority-Driven Flow Control Mechanism for Real-Time Traffic in Multiprocessor Networks,” IEEE Trans. Parallel and Distributed Systems, vol. 9, no. 7, pp. 664-678, July 1998.
[4] S.K. Baruah, N.K. Cohen, C.G. Plaxton, and D.A. Varvel, “Proportionate Progress: A Notion of Fairness in Resource Allocation,” STOC '93: Proc. 25th Ann. ACM Symp. Theory of Computing, pp. 345-354, 1993.
[5] E. Bini and G.C. Buttazzo, “Measuring the Performance of Schedulability Tests,” Real-Time Systems, vol. 30, nos. 1/2, pp. 129-154, 2005.
[6] T. Bjerregaard and S. Mahadevan, “A Survey of Research and Practices of Network-on-Chip,” ACM Computing Surveys, vol. 38, no. 1, p. 1, 2006.
[7] T. Chen, R. Raghavan, J. Dale, and E. Iwata, “Cell Broadband Engine Architecture and Its First Implementation: A Performance View,” IBM J. Research and Development, vol. 51, no. 5, pp. 559-572, 2005.
[8] J. Howard et al., “A 48-Core IA-32 Message-Passing Processor with DVFS in 45nm CMOS,” Proc. IEEE Int'l Solid-State Circuits Conf., 2010.
[9] K. Goossens, J. Dielissen, and A. Radulescu, “Aethereal Network on Chip: Concepts, Architectures, and Implementations,” IEEE Design and Test of Computers,, vol. 22, no. 5, pp. 414-421, Sept./Oct. 2005.
[10] S. Gopalakrishnan, L. Sha, and M. Caccamo, “Hard Real-Time Communication in Bus-Based Networks,” RTSS '04: Proc. 25th IEEE Int'l Real-Time Systems Symp., pp. 405-414, 2004.
[11] P. Holman and J.H. Anderson, “Adapting Pfair Scheduling for Symmetric Multiprocessors,” J. Embedded Computing, vol. 1, no. 4, pp. 543-564, 2005.
[12] J. Kleinberg and E. Tardos, Algorithm Design. Addison-Wesley Longman Publishing Co., Inc., 2005.
[13] J.P. Lehoczky and L. Sha, “Performance of Real-Time Bus Scheduling Algorithms,” SIGMETRICS Performance Evaluation Rev., vol. 14, no. 1, pp. 44-53, 1986.
[14] J. Li and M.W. Mutka, “Real-Time Virtual Channel Flow Control,” J. Parallel and Distributed Computing, vol. 32, no. 1, pp. 49-65, 1996.
[15] C.L. Liu and J.W. Layland, “Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment,” J. ACM, vol. 20, no. 1, pp. 46-61, 1973.
[16] C.D. Locke, D.R. Vogel, L. Lucas, and J.B. Goodenough, “Generic Avionics Software Specification,” Technical Report CMU/SEI-90-TR-8, Software Eng. Inst., Carnegie Mellon Univ., 1990.
[17] Z. Lu, A. Jantsch, and I. Sander, “Feasibility Analysis of Messages for On-Chip Networks Using Wormhole Routing,” ASP-DAC '05: Proc. Asia and South Pacific Design Automation Conf., pp. 960-964, 2005.
[18] M.D. Natale and A. Meschi, “Scheduling Messages with Earliest Deadline Techniques,” Real-Time Systems, vol. 20, no. 3, pp. 255-285, 2001.
[19] L.M. Ni and P.K. Mckinley, “A Survey of Wormhole Routing Techniques in Direct Networks,” Computer, vol. 26, no. 2, pp. 62-76, Feb. 1993.
[20] IBM Research “Cell BE Programming Tutorial,” IBM, 2007.
[21] Z. Shi and A. Burns, “Priority Assignment for Real-Time Wormhole Communication in On-Chip Networks,” RTSS '08: Proc. Real-Time Systems Symp., pp. 421-430, 2008.
[22] Z. Shi and A. Burns, “Real-Time Communication Analysis for On-Chip Networks with Wormhole Switching,” NOCS '08: Proc. Second ACM/IEEE Int'l Symp. Networks-on-Chip, pp. 161-170, 2008.
[23] K. Tindell, A. Burns, and A. Wellings, “Analysis of Hard Real-Time Communications,” Real-Time Systems, vol. 9, pp. 147-171, 1995.
[24] D. Zhu, D. Mosse, and R. Melhem, “Multiple-Resource Periodic Scheduling Problem: How Much Fairness Is Necessary,” Proc. 24th IEEE Int'l Real-Time Systems Symp., 2003.
298 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool