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Issue No. 09 - Sept. (2012 vol. 61)
ISSN: 0018-9340
pp: 1243-1255
Dong Wang , Inst. of Microelectron., Tsinghua Univ., Beijing, China
M. D. Ercegovac , UCLA Comput. Sci. Dept., Univ. of California, Los Angeles, CA, USA
We present a novel design of a radix-16 combined unit for complex division and square root in fixed-point format. A new digit-recurrence algorithm with two-step operand prescaling is developed for complex square root to avoid postscaling of the result. A combined recurrence algorithm is generalized and a scalable hardware architecture is proposed. Designs with different operand precision are implemented in Altera Stratix-II FPGA and cost and performance are evaluated and compared with reference designs of complex division or square root implemented combined or separately. The results show advantages of the proposed combined design in cost and performance.
prescalers, field programmable gate arrays, fixed point arithmetic, Altera Stratix-II FPGA, radix-16 combined complex division-square root, fixed-point format, digit-recurrence algorithm, two-step operand prescaling, hardware architecture, Algorithm design and analysis, Field programmable gate arrays, Table lookup, Hardware, Signal processing algorithms, Zirconium, Digital signal processing, radix-16 algorithms., Complex division, complex square root, digit-recurrence, operand prescaling, postscaling, combined design, field-programmable gate array (FPGA)

Dong Wang and M. D. Ercegovac, "A Radix-16 Combined Complex Division/Square Root Unit with Operand Prescaling," in IEEE Transactions on Computers, vol. 61, no. , pp. 1243-1255, 2012.
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