Issue No. 09 - Sept. (2012 vol. 61)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2011.138
Alejandro Valero , U.P.V., Valencia
Salvador Petit , University Politecnica de Valencia, Valencia
Julio Sahuquillo , University Politecnica de Valencia, Valencia
Pedro López , University Politecnica de Valencia, Valencia
José Duato , University Politecnica de Valencia, Valencia
SRAM and DRAM have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are not destructive. In contrast, DRAM cells provide higher density and minimal leakage energy since there are no paths within the cell from Vdd to ground. Recently, DRAM cells have been embedded in logic-based technology (eDRAM), thus overcoming the speed limit of typical DRAM cells. In this paper, we propose a hybrid n-bit macrocell that implements one SRAM cell and n-1 eDRAM cells. This cell is aimed at being used in an n-way set-associative first-level data cache. Architectural mechanisms (e.g., special writeback policies) have been devised to completely avoid refresh logic. Performance, energy, and area have been analyzed in detail. Experimental results show that using typical eDRAM capacitors, and compared to a conventional cache, a 4-way set-associative hybrid cache reduces both energy consumption and area up to 54 and 29 percent, respectively, while having negligible impact on performance (less than 2 percent).
Retention time, static and dynamic energy, static and dynamic memory cells, way prediction.
Alejandro Valero, Salvador Petit, Julio Sahuquillo, Pedro López, José Duato, "Design, Performance, and Energy Consumption of eDRAM/SRAM Macrocells for L1 Data Caches", IEEE Transactions on Computers, vol. 61, no. , pp. 1231-1242, Sept. 2012, doi:10.1109/TC.2011.138