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Issue No.08 - Aug. (2012 vol.61)
pp: 1189-1202
Ashur Rafiev , Newcastle University, Newcastle Upon Tyne
Andrey Mokhov , Newcastle University, Newcastle Upon Tyne
Frank P. Burns , Newcastle University, Newcastle Upon Tyne
Julian P. Murphy , Newcastle University, Newcastle Upon Tyne
Albert Koelmans , Newcastle University, Newcastle Upon Tyne
Alex Yakovlev , Newcastle University, Newcastle Upon Tyne
The choice of radix is crucial for multivalued logic synthesis. Practical examples, however, reveal that it is not always possible to find the optimal radix when taking into consideration actual physical parameters of multivalued operations. In other words, each radix has its advantages and disadvantages. Our proposal is to synthesize logic in different radices, so it may benefit from their combination. The theory presented in this paper is based on Reed-Muller expansions over Galois field arithmetic. The work aims to first estimate the potential of the new approach and to second analyze its impact on circuit parameters down to the level of physical gates. The presented theory has been applied to real-life examples focusing on cryptographic circuits where Galois Fields find frequent application. The benchmark results show that the approach creates a new dimension for the trade-off between circuit parameters and provides information on how the implemented functions are related to different radices.
Automatic synthesis, multiple valued logic, data encryption.
Ashur Rafiev, Andrey Mokhov, Frank P. Burns, Julian P. Murphy, Albert Koelmans, Alex Yakovlev, "Mixed Radix Reed-Muller Expansions", IEEE Transactions on Computers, vol.61, no. 8, pp. 1189-1202, Aug. 2012, doi:10.1109/TC.2011.124
[1] M. Gao, J.-H. Jiang, Y. Jiang, Y. Li, A. Mishchenko, S. Sinha, T. Villa, and R. Brayton, "Optimization of Multi-Valued Multi-Level Networks," Proc. Int'l Symp. Multiple-Valued Logic (ISMVL '02), pp. 168-77, May 2002.
[2] W. Bainbridge, W. Toms, D. Edwards, and S. Furber, "Delay-Insensitive, Point-to-Point Interconnect Using m-of-n Codes," Proc. Ninth Int'l Symp. Asynchronous Circuits and Systems (ASYNC '03), 2003.
[3] Intrinsity, Inc., Technology White Papers,, ch. 8: N-ary Circuits: Robust Gate Design, 2006.
[4] A. Bystrov, D. Sokolov, A. Yakovlev, and A. Koelmans, "Balancing Power Signature in Secure Systems," Proc. 14th UK Asynchronous Forum, 2003.
[5] Y. Baba, A. Miyamoto, N. Homma, and T. Aoki, "Multiple-Valued Constant-Power Adder for Cryptographic Processors," Proc. Int'l Symp. Multiple-Valued Logic (ISMVL '09), 2009.
[6] C. D'Alessandro, D. Shang, A.V. Bystrov, A. Yakovlev, and O.V. Maevsky, "Multiple-Rail Phase-Encoding for NoC," Proc. Int'l Symp. Advanced Research in Asynchronous Circuits and Systems (ASYNC), pp. 107-116, 2006.
[7] P.B. McGee, M.Y. Agyekum, M.A. Mohamed, and S.M. Novick, "A Level-Encoded Transition Signaling Protocol for High-Throughput Asynchronous Global Communication," Proc. Int'l Symp. Asynchronous Circuits and Systems (ASYNC '08), 2008.
[8] A. Rafiev, J. Murphy, D. Sokolov, and A. Yakovlev, "Conversion Driven Design of Binary to Mixed Radix Circuits," Proc. Int'l Conf. Computer Design (ICCD), 2008.
[9] W.B. Toms, D.A. Edwards, and A. Bardsley, "Synthesising Heterogeneously Encoded Systems," Proc. 12th IEEE Int'l Symp. Asynchronous Circuits and Systems (ASYNC '06), 2006.
[10] D. Green and I. Taylor, "Multiple-Valued Switching Circuit Design by Means of Generalized Reed-Muller Expansions," Digital Processes, vol. 2, pp. 63-81, 1976.
[11] D. Pradhan, "A Theory of Galois Switching Functions," IEEE Trans. Computers, vol. 27, no. 3, pp. 239-248, Mar. 1978.
[12] D. Green, "Reed-Muller Expansions with Fixed and Mixed Polarities over GF(4)," IEE Proc. E Computers and Digital Techniques, vol. 137, no. 5, pp. 380-388, Sept. 1990.
[13] S. Rahardja and B. Falkowski, "Efficient Algorithm to Calculate Reed-Muller Expansions over GF(4)," IEE Proc. Circuits, Devices and Systems, vol. 148, no. 6, pp. 289-295, Dec. 2001.
[14] D. Jankovic, R.S. Stankovic, and C. Moraga, "Optimization of GF(4) Expressions Using the Extended Dual Polarity Property," Proc. Int'l Symp. Multiple-Valued Logic (ISMVL '03), p. 50, 2003.
[15] B.J. Falkowski and C.C. Lozano, "Quaternary Fixed-Polarity Reed-Muller Expansion Computation through Operations on Disjoint Cubes and Its Comparison with Other Methods," Computers and Electrical Eng., vol. 31, pp. 112-131, 2005.
[16] A. Rafiev, J.P. Murphy, and A. Yakovlev, "Quaternary Reed-Muller Expansions of Mixed Radix Arguments in Cryptographic Circuits," Proc. 39th Int'l Symp. Multiple-Valued Logic (MVL), 2009.
[17] T.C. Bartee and D.I. Schneider, "Computation with Finite Fields," Information Control, vol. 6, pp. 79-88, June 1963.
[18] H. Eves, Elementary Matrix Theory. Dover Publications, 1980.
[19] M. Renaudin and F. Bouesse, "High Security Smartcards," Proc. Design, Automation and Test in Europe Conf. and Exhibition (DATE '04), 2004.
[20] P. Kocher, J. Jaffe, and B. Jun, "Differential Power Analysis," Proc. Int'l Conf. Cryptology (CRYPTO), pp. 388-397, 1999.
[21] S. Moore, R. Anderson, P. Cunningham, R. Mullins, and G. Taylor, "Improving Smart Card Security Using Self-Timed Circuits," Proc. Int'l Symp. Asynchronous Circuits and Systems, pp. 211-218, 2002.
[22] D. Sokolov, J. Murphy, A. Bystrov, and A. Yakovlev, "Design and Analysis of Dual-Rail Circuits for Security Applications," IEEE Trans. Computers, vol. 54, no. 4, pp. 449-460, Apr. 2005.
[23] I. David, R. Ginosar, and M. Yoeli, "An Efficient Implementation of Boolean Functions as Self-Timed Circuits," IEEE Trans. Computers, vol. 41, no. 1, pp. 2-11, Jan. 1992.
[24] "Cryptographic Processing and Processors," Newcastle Univ., UK Patent No. 0719455.8, Oct. 2008.
[25] A. Rafiev, J. Murphy, and A. Yakovlev, "RTL Implementations of GF(2) and GF(4) Arithmetic Components," technical report, Newcastle Univ., 2008.
[26] S. Guilley, P. Hoogvorst, Y. Mathieu, R. Pacalet, and J. Provost, "CMOS Structures Suitable for Secured Hardware," Proc. Design, Automation and Test in Europe Conf. and Exhibition (DATE '04), 2004.
[27] Federal Information Processing Standards FIPS 140-3 (Draft), Nat'l Inst. of Standards and Tech nology, 2008.
[28] F. Burns, A. Bystrov, A. Koelmans, and A. Yakovlev, "Design and Security Evaluation of Balanced 1-of-n Circuits," technical report, School of EECE, Newcastle Univ., Mar. 2010.
[29] G. Yee and C. Sechen, "Dynamic Logic Synthesis," Proc. IEEE Custom Integrated Circuits Conf. (CICC '97), 1997.
[30] Specification for the Advanced Encryption Standard (AES), Fed. Information Processing Standards Publication 197, Nov. 2001.
[31] R. Anderson, E. Biham, and L. Knudsenin, "Serpent and Smartcards," Proc. Int'l Conf. Smart Card Research and Applications (CARDIS '98), pp. 257-264, 2000.
[32], 2011.
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