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Issue No.08 - Aug. (2012 vol.61)
pp: 1110-1126
A. G. Andreou , Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA
Beginning with Amdahl's law, we derive a general objective function that links parallel processing performance gains at the system level, to energy and delay in the subsystem microarchitecture structures. The objective function employs parameterized models of computation and communication to represent the characteristics of processors, memories, and communications networks. The interaction of the latter microarchitectural elements defines global system performance in terms of energy-delay cost. Following the derivation, we demonstrate its utility by applying it to the problem of Chip Multiprocessor (CMP) architecture exploration. Given a set of application and architectural parameters, we solve for the optimal CMP architecture for six different architectural optimization examples. We find the parameters that minimize the total system cost, defined by the objective function under the area constraint of a single die. The analytical formulation presented in this paper is general and offers the foundation for the quantitative and rapid evaluation of computer architectures under different constraints including that of single die area.
parallel processing, microprocessor chips, single die area, Amdahl law, general objective function, parallel processing performance, system level, subsystem microarchitecture structures, memories, communications networks, microarchitectural elements, global system performance, energy-delay cost, chip multiprocessor architecture exploration, architectural parameters, optimal CMP architecture, architectural optimization, computer architectures, Delay, Program processors, Computer architecture, Parallel processing, Hidden Markov models, Algorithm design and analysis, Optimization, chip-multiprocessor architecture., Modeling, evaluation, design exploration, and optimization of multiprocessor systems
A. G. Andreou, "Beyond Amdahl's Law: An Objective Function That Links Multiprocessor Performance Gains to Delay and Energy", IEEE Transactions on Computers, vol.61, no. 8, pp. 1110-1126, Aug. 2012, doi:10.1109/TC.2011.169
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