The Community for Technology Leaders
RSS Icon
Issue No.07 - July (2012 vol.61)
pp: 986-998
Kunal P. Ganeshpure , University of Massachusetts, Amherst
Alodeep Sanyal , University of Massachusetts, Amherst
Sandip Kundu , University of Massachusetts, Amherst
Computation of peak supply current is central to power rail design and analysis of power supply switching noise. Traditionally, peak switching current from all CMOS gates is added together to compute peak supply current. This approach can be improved significantly if temporal and Boolean relationships are taken into consideration. Previously, it was shown that worst case switching current in a subset of gates may imply that some other gates may not have the worst case switching condition due to logical relationship between input patterns of a gate. In this paper, we also take integer gate delays into consideration to show that gate switching events may be spaced out in time leading to lower peak current. Further, it is found that taking gate delays into account actually simplifies the size of individual problem instances to be solved, leading to both a faster and more accurate solution. Finally, we compare peak current waveform generated by the proposed solver against SPICE simulation to demonstrate effectiveness of the proposed solution.
Peak current analysis, power supply current, pattern generation, integer linear program, gate delay.
Kunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu, "A Pattern Generation Technique for Maximizing Switching Supply Currents Considering Gate Delays", IEEE Transactions on Computers, vol.61, no. 7, pp. 986-998, July 2012, doi:10.1109/TC.2011.128
[1] C. Tirumurti, S. Kundu, S. Sur-Kolay, and Y.-S. Chang, “A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuits,” Proc. Conf. Design, Automation and Test in Europe (DATE), pp. 1078-1083, 2004.
[2] D. Suryanarayana, R. Hsiao, T. Gall, and J. McCreary, “Enhancement of Flip-Chip Fatigue Life by Encapsulation,” IEEE Trans. Components, Packaging, and Manufacturing Technology, vol. 14, no. 1, pp. 218-223, Mar. 1991.
[3] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicron CMOS Circuits,” Proc. IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003.
[4] H. Kriplani, F.N. Najm, and I.N. Hajj, “Pattern Independent Maximum Current Estimation in Power and Ground Buses of CMOS VLSI Circuits: Algorithms, Signal Correlations, and Their Resolution,” IEEE Trans. Computer-Aided Design, vol. 14, no. 8, pp. 998-1012, Aug. 1995.
[5] A. Nabavi-Lishi and N. Rumin, “Delay and Bus Current Evaluation in CMOS Logic Circuits,” Proc. IEEE/ACM Int'l Conf. Computer-Aided Design, pp. 198-203, 1992.
[6] U. Jagau, “SIMCURRENT-An Efficient Program for the Estimation of the Current Flow of Complex CMOS Circuits,” Proc. IEEE/ACM Int'l Conf. Computer-Aided Design, pp. 208-211, 1988.
[7] S. Chowdhury and J. Barkatullah, “Estimation of Maximum Currents in MOS IC Logic Circuits,” IEEE Trans. Computer-Aided Design, vol. 9, no. 6, pp. 642-654, June 1990.
[8] K. Ganeshpure, A. Sanyal, and S. Kundu, “A Pattern Generation Technique for Maximizing Power Supply Currents,” Proc. IEEE Int'l Conf. Computer Design (ICCD), pp. 387-392, 2006.
[9] Y. Jiang, A. Krstic, and K. Cheng, “Estimation for Maximum Instantaneous Current through Supply Lines for CMOS Circuits,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 8, no. 1, pp. 61-73, Feb. 2000.
[10] D. Chai and A. Kuehlmann, “Circuit-Based Preprocessing of ILP and Its Applications in Leakage Minimization and Power Estimation,” Proc. IEEE Int'l Conf. Computer Design (ICCD), pp. 387-392, 2004.
[11] S. Devadas, K. Keutzer, and J. White, “Estimation of Power Dissipation in CMOS Combinational Circuits Using Boolean Function Manipulation,” IEEE Trans. Computer-Aided Design, vol. 11, no. 3, pp. 373-383, Mar. 1992.
[12] F. Najm and M. Zhang, “Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuits,” Proc. Design Automation Conf., pp. 623-627, 1995.
[13] C. Wang and K. Roy, “Maximum Power Estimation for CMOS Circuits Using Deterministic and Statistic Approaches,” Proc. Int'l Conf. VLSI Design pp. 364-369, 1995.
[14] S. Manich and J. Figueras, “Maximizing the Weighted Switching Activity in Combinational CMOS Circuits under Variable Delay Model,” Proc. European Design and Test Conf., pp. 597-602, 1997.
[15] Q. Wu, Q. Qiu, and M. Pedram, “Estimation of Peak Power Dissipation in VLSI Circuits Using the Limiting Distributions of Extreme Order Statistics,” IEEE Trans. Computer Aided Design of Integrated Circuits and Systems, vol. 20, no. 8, pp. 942-956, Aug. 2001.
[16] M. Hsiao, E. Rudnick, and J. Patel, “Peak Power Estimation of VLSI Circuits: New Peak Power Measures,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 8, no. 4, pp. 435-439, Aug. 2000.
[17] S. Gupta and F. Najm, “Energy and Peak-Current Per-Cycle Estimation at RTL,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 11, no. 4, pp. 525-537, Aug. 2003.
[18] A. Sagahyroon and F. Aloul, “Using SAT-Based Techniques in Power Estimation,” Microelectronics J., vol. 38, nos. 6/7, pp. 706-715, 2007.
[19] F. Aloul, A. Ramani, I. Markov, and K. Sakallah, “Generic ILP versus Specialized 0-1 ILP: An Update,” Proc. Int'l Conf. Computer Aided Design, pp. 450-457, 2002.
[20] D. Chai and A. Kuehlmann, “A Fast Pseudo-Boolean Constraint Solver,” IEEE Trans. Computer-Aided Design, vol. 24, no. 3, pp. 305-317, Mar. 2005.
[21] N. Een and N. Sorensson, “An Extensible SAT-Solver,” Proc. Int'l Conf. Theory and Applications of Satisfiability Testing (SAT), pp. 502-508, 2003.
[22] ILOG CPLEX,, 2011.
[23] Y. Jiang and K. Cheng, “Vector Generation for Power Supply Noise Estimation and Verification of Deep Submicron Designs,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 9, no. 2, pp. 329-340, Apr. 2001.
[24] A. Krstic, Y. Jiang, and K. Cheng, “Pattern Generation for Delay Testing and Dynamic Timing Analysis Considering Power Supply Noise Effects,” IEEE Trans. Computer-Aided Design, vol. 20, no. 3, pp. 416-425, Mar. 2001.
[25] HSPICE User's Manual: Verification/ AMSVerification/CircuitSimulation/ HSPICE/Pagesdefault.aspx, 2011.
[26] R. Fortet, “Applications De L'Algebre De Boole en Recherche Operationelle,” Revue Francaise de Recherche Operationelle, vol. 4, pp. 17-26, 1960.
[27] T. Larrabee, “Test Pattern Generation Using Boolean Satisfiability,” IEEE Trans. Computer-Aided Design, vol. 11, no. 1, pp. 4-15, Jan. 1992.
[28] GNU Linear Programming Kit:, 2011.
[29] M. Hrishikesh, N. Jouppi, K. Farkas, D. Burger, S. Keckler, and P. Shivakumar, “The Optimal Logic Depth per Pipeline Stage Is 6 to 8 FO4 Inverter Delays,” ACM SIGARCH Computer Architecture News, vol. 30, no. 2, pp. 14-24, 2002.
[30] N.H. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, third ed. Addison Wesley, Jan. 2005.
[31] Dell PowerEdge Server: global/ products/pedge/en2800_specs.pdf, 2011.
14 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool