Issue No. 07 - July (2012 vol. 61)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2011.128
Kunal P. Ganeshpure , University of Massachusetts, Amherst
Alodeep Sanyal , University of Massachusetts, Amherst
Sandip Kundu , University of Massachusetts, Amherst
Computation of peak supply current is central to power rail design and analysis of power supply switching noise. Traditionally, peak switching current from all CMOS gates is added together to compute peak supply current. This approach can be improved significantly if temporal and Boolean relationships are taken into consideration. Previously, it was shown that worst case switching current in a subset of gates may imply that some other gates may not have the worst case switching condition due to logical relationship between input patterns of a gate. In this paper, we also take integer gate delays into consideration to show that gate switching events may be spaced out in time leading to lower peak current. Further, it is found that taking gate delays into account actually simplifies the size of individual problem instances to be solved, leading to both a faster and more accurate solution. Finally, we compare peak current waveform generated by the proposed solver against SPICE simulation to demonstrate effectiveness of the proposed solution.
Peak current analysis, power supply current, pattern generation, integer linear program, gate delay.
K. P. Ganeshpure, A. Sanyal and S. Kundu, "A Pattern Generation Technique for Maximizing Switching Supply Currents Considering Gate Delays," in IEEE Transactions on Computers, vol. 61, no. , pp. 986-998, 2011.