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Issue No. 05 - May (2012 vol. 61)
ISSN: 0018-9340
pp: 593-606
J. Duato , Dept. de Informdtica de Sist. y Comput., Univ. Politec. de Valencia, València, Spain
J. M. Garcia , Dept. de Ing. y Tecnol. de Comput., Univ. de Murcia, Murcia, Spain
A. Robles , Dept. de Informdtica de Sist. y Comput., Univ. Politec. de Valencia, València, Spain
M. E. Acacio , Dept. de Ing. y Tecnol. de Comput., Univ. de Murcia, Murcia, Spain
M. E. Gomez , Dept. de Informdtica de Sist. y Comput., Univ. Politec. de Valencia, València, Spain
R. Fernandez-Pascual , Dept. de Ing. y Tecnol. de Comput., Univ. de Murcia, Murcia, Spain
B. Cuesta , Dept. de Informdtica de Sist. y Comput., Univ. Politec. de Valencia, València, Spain
A. Ros , Dept. de Informdtica de Sist. y Comput., Univ. Politec. de Valencia, València, Spain
ABSTRACT
One cost-effective way to meet the increasing demand for larger high-performance shared-memory servers is to build clusters with off-the-shelf processors connected with low-latency point-to-point interconnections like HyperTransport. Unfortunately, HyperTransport addressing limitations prevent building systems with more than eight nodes. While the recent High-Node Count HyperTransport specification overcomes this limitation, recently launched twelve-core Magny-Cours processors have already inherited it and provide only 3 bits to encode the pointers used by the directory cache which they include to increase the scalability of their coherence protocol. In this work, we propose and develop an external device to extend the coherence domain of Magny-Cours processors beyond the 8-node limit while maintaining the advantages provided by the directory cache. Evaluation results for systems with up to 32 nodes show that the performance offered by our solution scales with the number of nodes, enhancing the directory cache effectiveness by filtering additional messages. Particularly, we reduce execution time by 47 percent in a 32-die system with respect to the 8-die Magny-Cours configuration.
INDEX TERMS
shared memory systems, cache storage, Internet, microprocessor chips, protocols, Internet, magny-cours cache coherence, arger high-performance shared-memory servers, off-the-shelf processors, low-latency point-to-point interconnections, hypertransport, twelve-core magny-cours processors, coherence protocol, directory cache, traffic filtering, Coherence, Probes, Program processors, Protocols, Servers, Scalability, Proposals, traffic filtering., High-performance computing, shared memory, cache coherence, directory protocol, coherence extension, scalability
CITATION
J. Duato, J. M. Garcia, A. Robles, M. E. Acacio, M. E. Gomez, R. Fernandez-Pascual, B. Cuesta, A. Ros, "Extending Magny-Cours Cache Coherence", IEEE Transactions on Computers, vol. 61, no. , pp. 593-606, May 2012, doi:10.1109/TC.2011.65
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