Issue No. 04 - April (2012 vol. 61)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2011.26
Jeyavijayan Rajendran , Polytechnic Institute of New York University, Brooklyn
Ramesh Karri , Polytechnic Institute of New York University, Brooklyn
Harika Manem , Polytechnic Institute of New York University, Brooklyn
Garrett S. Rose , Polytechnic Institute of New York University, Brooklyn
Researchers have claimed that the memristor, the fourth fundamental circuit element, can be used for computing. In this work, we utilize memristors as weights in the realization of low-power Field Programmable Gate Arrays (FPGAs) using threshold logic which is necessary not only for low power embedded systems, but also realizing biological applications using threshold logic. Boolean functions, which are subsets of threshold functions, can be implemented using the proposed Memristive Threshold Logic (MTL) gate, whose functionality can be configured by changing the weights (memristance). A CAD framework is also developed to map the weights of a threshold gate to corresponding memristance values and synthesize logic circuits using MTL gates. Performance of the MTL gates at the circuit and logic levels is also evaluated using this CAD framework using ISCAS-85 combinational benchmarking circuits. This work also provides solutions based on device options and refreshing memristance, against drift in memristance, which can be a potential problem during operation. Comparisons with the existing CMOS look-up-table (LUT) and capacitor threshold logic (CTL) gates show that MTL gates exhibit less energy-delay product by at least 90 percent.
Memristor, threshold logic, memristance drift.
Jeyavijayan Rajendran, Ramesh Karri, Harika Manem, Garrett S. Rose, "An Energy-Efficient Memristive Threshold Logic Circuit", IEEE Transactions on Computers, vol. 61, no. , pp. 474-487, April 2012, doi:10.1109/TC.2011.26