Issue No. 02 - February (2012 vol. 61)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2010.254
Chi-Neng Wen , National Chung-Cheng University
Shu-hsuan Chou , National Chung-Cheng University, Chia-Yi
Chien-Chih Chen , National Chiao-Tung University, Hsin-Chu
Tien-Fu Chen , National Chiao-Tung University, Hsin-Chu
Traditional debugging methodologies are limited in their ability to provide debugging support for many-core parallel programming. Synchronization problems or bugs due to race conditions are particularly difficult to detect with existing debugging tools. Most traditional debugging approaches rely on globally synchronized signals, but these pose their own problems in terms of scalability. The first contribution of this paper is to propose a novel non-uniform debugging architecture (NUDA) based on a ring interconnection schema. Our approach makes hardware-assisted debugging both feasible and scalable for many-core processing scenarios. The key idea is to distribute the debugging support structures across a set of hierarchical clusters while avoiding address overlap. The design strategy allows the address space to be monitored using non-uniform protocols. Our second contribution is to propose a nonintrusive approach to lockset-based race detection supported by the NUDA. A non-uniform page-based monitoring cache in each NUDA node is used to keep track of the access footprints. The union of all the caches can serve as a race detection probe without disturbing execution ordering. Using the proposed approach, we show that parallel race bugs can be precisely captured, and that most false-positive alerts can be efficiently eliminated at an average slowdown cost of only 1.4-3.6 percent. The net hardware cost is relatively low, so that the NUDA can easily be scaled to increasingly complex many-core systems.
NUDA, lockset, data race, nonintrusive, manycore, debugging.
S. Chou, C. Wen, T. Chen and C. Chen, "NUDA: A Non-Uniform Debugging Architecture and Nonintrusive Race Detection for Many-Core Systems," in IEEE Transactions on Computers, vol. 61, no. , pp. 199-212, 2010.