Issue No. 02 - February (2012 vol. 61)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2010.261
Haridimos T. Vergos , University of Patras, Patras
Giorgos Dimitrakopoulos , University of West Macedonia, Kozani
Two architectures for modulo 2^n+1 adders are introduced in this paper. The first one is built around a sparse carry computation unit that computes only some of the carries of the modulo 2^n+1 addition. This sparse approach is enabled by the introduction of the inverted circular idempotency property of the parallel-prefix carry operator and its regularity and area efficiency are further enhanced by the introduction of a new prefix operator. The resulting diminished-1 adders can be implemented in smaller area and consume less power compared to all earlier proposals, while maintaining a high operation speed. The second architecture unifies the design of modulo 2^n\pm 1 adders. It is shown that modulo 2^n+1 adders can be easily derived by straightforward modifications of modulo 2^n-1 adders with minor hardware overhead.
Modulo arithmetic, residue number system (RNS), parallel-prefix carry computation, computer arithmetic, VLSI.
H. T. Vergos and G. Dimitrakopoulos, "On Modulo 2^n+1 Adder Design," in IEEE Transactions on Computers, vol. 61, no. , pp. 173-186, 2010.