Issue No.02 - February (2012 vol.61)
Ashkan Hosseinzadeh Namin , University of Waterloo, Waterloo
Huapeng Wu , University of Windsor, Windsor
Majid Ahmadi , University of Windsor, Windsor
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TC.2010.218
Normal basis has been widely used for the representation of binary field elements mainly due to its low-cost squaring operation. Optimal normal basis type II is a special class of normal basis exhibiting very low multiplication complexity and is considered as a safe choice for hardware implementation of cryptographic applications. In this paper, high-speed architectures for binary field multiplication using reordered normal basis are proposed, where reordered normal basis is referred to as a certain permutation of optimal normal basis type II. Complexity comparison shows that the proposed architectures are faster compared to previously presented architectures in the open literature using either an optimal normal basis type II or a reordered normal basis. One advantage of the new word-level architectures is that the critical path delay is a constant (not a function of word size). This enables the multipliers to operate at very high clock rates regardless of the field size or the number of words. Hardware implementation of some practical size multipliers for elliptic curve cryptography is also included.
Finite field, binary field, optimal normal basis type II, reordered normal basis, multiplication algorithm, multiplier, hardware.
Ashkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmadi, "High-Speed Architectures for Multiplication Using Reordered Normal Basis", IEEE Transactions on Computers, vol.61, no. 2, pp. 164-172, February 2012, doi:10.1109/TC.2010.218