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Issue No.12 - December (2011 vol.60)
pp: 1744-1758
Cristiana Bolchini , Politecnico di Milano, Milano
Antonio Miele , Politecnico di Milano, Milano
Chiara Sandionigi , Politecnico di Milano, Milano
This paper presents a novel design flow for the implementation of digital systems onto SRAM-based FPGAs with soft error mitigation properties. Traditional fault detection/tolerance techniques are coupled with the device dynamic reconfiguration property to achieve soft error mitigation capabilities, and are applied to the single component, to groups of components or to the entire system, based on the most convenient trade-off with respect to a set of parameters. The design flow performs a two-steps multiobjective design space exploration, driven by a cost function taking into account resource utilization, area, and reconfiguration time. A floorplanning based on precise FPGA resource models is introduced to guarantee the feasibility of the hardened solution, identifying a convenient mapping onto the heterogeneous reconfigurable fabric. Experimental results show that the achieved solutions, aimed at achieving a prompt, "on demand” recovery when fault occurs, are characterized by a reduction in reconfiguration time that is higher than 80 percent, a significant improvement with respect to classical solutions.
Soft errors, FPGAs, reliability, design space exploration.
Cristiana Bolchini, Antonio Miele, Chiara Sandionigi, "A Novel Design Methodology for Implementing Reliability-Aware Systems on SRAM-Based FPGAs", IEEE Transactions on Computers, vol.60, no. 12, pp. 1744-1758, December 2011, doi:10.1109/TC.2010.281
[1] E. Normand, “Single Event Upset at Ground Level,” IEEE Trans. Nuclear Science, vol. 43, nos. 1-6, pp. 2742-2750, Dec. 1996.
[2] R. Katz, K. LaBel, J.J. Wang, B. Cronquist, R. Koga, S. Penzin, and G. Swift, “Radiation Effectcs on Current Field Programmable Technologies,” IEEE Trans. Nuclear Science, vol. 44, no. 6, pp. 1945-1956, Dec. 1997.
[3] Actel Corp., Actel RTAX-S/SL FPGAs, RTAXSpib.pdf, 2007.
[4] R. Roosta, “A Comparison of Radiation-Hard and Radiation-Tolerant FPGAs for Space Applications,” Technical Report JPL D-31228, NASA-Jet Propulsion Laboratory, 2004.
[5] Atmel Corp., Rad Hard Reprogrammable FPGA-ATF280E, 2007.
[6] Lattice Semiconductor Corp, FPGA Devices, index.cfm, 2010.
[7] Actel Corp., SX Family FPGAs RadTolerant and HiRel, 2005.
[8] S. Rezgui, J. Wang, E.C. Tung, J. McCollum, and B. Cronquist, “New Methodologies for SET Characterization and Mitigation in Flash-Based FPGAs,” IEEE Trans. Nuclear Science, vol. 54, nos. 1-6, pp. 2512-2524, Dec. 2007.
[9] N. Battezzati, S. Gerardin, A. Manuzzato, A. Paccagnella, S. Rezgui, L. Sterpone, and M. Violante, “On the Evaluation of Radiation-Induced Transient Faults in Flash-Based FPGAs,” Proc. IEEE Int'l On-Line Testing Symp., pp. 135-140, 2008.
[10] Xilinx Inc, TMRTool, collateral tmrtool_sellsheet_wr.pdf, 2006.
[11] F.L. Kastensmidt, L. Sterpone, L. Carro, and M. Sonza Reorda, “On the Optimal Design of Triple Modular Redundancy Logic for SRAM-Based FPGAs,” Proc. Conf. Design, Automation and Test in Europe, pp. 1290-1295, 2005.
[12] C. Pilotto, J.R. Azambuja, and F.L. Kastensmidt, “Synchronizing Triple Modular Redundant Designs in Dynamic Partial Reconfiguration Applications,” Proc. Symp. Integrated Circuits and System Design, pp. 199-204, 2008.
[13] J.R. Azambuja, F. Sousa, L. Rosa, and F.L. Kastensmidt, “Evaluating Large Grain TMR and Selective Partial Reconfiguration for Soft Error Mitigation in SRAM-Based FPGAs,” Proc. IEEE Int'l On-Line Testing Symp., pp. 101-106, 2009.
[14] P.K. Lala and B.K. Kumar, “An FPGA Architecture with Built-in Error Correction Capability,” Proc. ACM/SIGDA Int'l Symp. Field Programmable Gate Arrays, p. 245, 2003.
[15] C. Bolchini, F. Salice, D. Sciuto, and R. Zavaglia, “An Integrated Design Approach for Self-Checking FPGAs,” Proc. IEEE Int'l Symp. Defect and Fault Tolerance in Very Large-Scale Integration (VLSI) Systems, pp. 443-450, 2003.
[16] N. Rollins, M. Wirthlin, M. Caffrey, and P. Graham, “Evaluating TMR Techniques in the Presence of Single Event Upsets,” Proc. Int'l Conf. Military and Aerospace Programmable Logic Devices, p. 63, 2006.
[17] C. Carmichael, Triple Module Redundancy Design Techniques for Virtex FPGAs, Xilinx Application Notes, vol. 197, 2006.
[18] C. Bolchini, A. Miele, and M. Santambrogio, “TMR and Partial Dynamic Reconfiguration to Mitigate SEU Faults in FPGAs,” Proc. IEEE Int'l Symp. Defect and Fault-Tolerance in Very Large-Scale Integration (VLSI) Systems, pp. 87-95, 2007.
[19] C. Bolchini, D. Quarta, and M. Santambrogio, “SEU Mitigation for SRAM-Based FPGAs through Dynamic Partial Reconfiguration,” Proc. ACM/IEEE Great Lake Symp. Very Large-Scale Integration (VLSI), pp. 55-60, 2007.
[20] C. Bolchini and A. Miele, “Design Space Exploration for the Design of Reliable SRAM-Based FPGA Systems,” Proc. IEEE Int'l Symp. Defect and Fault-Tolerance in Very Large-Scale Integration (VLSI) Systems, pp. 332-340, 2008.
[21] C. Carmichael, M. Caffrey, and A. Salazar, Correcting Single-Event Upsets through Virtex Partial Configuration, Xilinx App. Notes, vol. 216, 2000.
[22] D.K. Pradhan, Fault-Tolerant Computing: Theory and Techniques. Prentice-Hall, Inc., 1986.
[23] S. D'Angelo, C. Metra, S. Pastore, A. Pogutz, and G.R. Sechi, “Fault-Tolerant Voting Mechanism and Recovery Scheme for TMR FPGA-Based Systems,” IEEE Defect and Fault-Tolerance in Very Large-Scale Integration (VLSI) Systems, pp. 233-240, 1998.
[24] P.K. Samudrala, J. Ramos, and S. Katkoori, “Selective Triple Modular Redundancy (STMR) Based Single-Event Upset (SEU) Tolerant Synthesis for Fpgas,” IEEE Trans. Nuclear Science, vol. 51, no. 5, pp. 2957-2969, Oct. 2004.
[25] B. Pratt, M. Caffrey, P. Graham, K. Morgan, and M. Wirthlin, “Improving FPGA Design Robustness with Partial TMR,” Proc. IEEE Int'l Reliability Physics Symp., pp. 226-232, 2006.
[26] F.L. Kastensmidt, G. Neuberger, R. Hentschke, L. Carro, and R. Reis, “Designing Fault-Tolerant Techniques for SRAM-Based FPGAs,” Design and Test of Computers, vol. 21, no. 6, pp. 552-562, Nov./Dec. 2004.
[27] H.R. Zarandi, S.G. Miremadi, C. Argyrides, and D.K. Pradhan, “Fast SEU Detection and Correction in LUT Configuration Bits for SRAM-Based FPGAs,” Proc. IEEE Reconfigurable Architecture Workshop, 2007.
[28] L. Sterpone and M. Violante, “A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs,” Computers, vol. 55, no. 6, pp. 732-744, June 2006.
[29] L. Sterpone, N. Battezzati, and M. Violante, “A New Placement Algorithm for the Optimization of Fault Tolerant Circuits on Reconfigurable Devices,” Proc. Workshop Radiation Effects and Fault Tolerance Nanometer Technologies, pp. 347-352, 2008.
[30] Xilinx Inc., Spartan-3 FPGA Family Data Sheet, 2008.
[31] Xilinx Inc., Virtex-II Platform FPGAs: Complete Data Sheet, 2007.
[32] Xilinx Inc., Virtex-4 FPGA Configuration User Guide, 2009.
[33] Xilinx Inc., Virtex-5 FPGA Configuration User Guide, 2009.
[34] L. Singhal and E. Bozorgzadeh, “Multi-Layer Floorplanning on a Sequence of Reconfigurable Designs,” Proc. Int'l Conf. Field Programmable Logic and Applications, pp. 1-8, Aug. 2006.
[35] L. Cheng and M.D.F. Wong, “Floorplan Design for Multimillion Gate FPGAs,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 12, pp. 2795-2805, Dec. 2006.
[36] P. Banerjee, S. Sur-Kolay, and A. Bishnu, “Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 5, pp. 651-661, May 2009.
[37] D. Nikolos, “Self-Testing Embedded Two-Rail Checkers,” J. Electronic Testing, Theory and Applications, vol. 12, nos. 1/2, pp. 69-79, 1998.
[38] K. Deb, A. Pratap, S. Agarwal, and T. Meyarivan, “A Fast and Elitist Multiobjective Genetic Algorithm: NSGA-II,” IEEE Trans. Evolutionary Computation, vol. 6, no. 2, pp. 182-197, Apr. 2002.
[39] S.M. Sait and H. Youssef, Very Large-Scale Integration (VLSI) Physical Design Automation: Theory and Practice. World Scientific Publishing Company, 1999.
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